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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug c/108654] New: Incorrect codegen of RVV GCC Date: Fri, 03 Feb 2023 08:20:07 +0000 [thread overview] Message-ID: <bug-108654-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108654 Bug ID: 108654 Summary: Incorrect codegen of RVV GCC Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: juzhe.zhong at rivai dot ai Target Milestone: --- #include "riscv_vector.h" void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int cond) { vint8m1_t v = *(vint8m1_t*)in; *(vint8m1_t*)out = v; vbool8_t v3 = *(vbool8_t*)in; *(vbool8_t*)(out + 200) = v3; vbool16_t v4 = *(vbool16_t *)in; *(vbool16_t *)(out + 300) = v4; } ASM: foo5_3: csrr t0,vlenb slli t1,t0,1 csrr a5,vlenb sub sp,sp,t1 slli a3,a5,1 vl1re8.v v24,0(a0) add a3,a3,sp vs1r.v v24,0(a1) addi a4,a1,800 sub a5,a3,a5 vsetvli a3,zero,e8,m1,ta,ma vsm.v v24,0(a4) vs1r.v v24,0(a5) addi a1,a1,1200 csrr t0,vlenb slli t1,t0,1 vsetvli a5,zero,e8,mf2,ta,ma vsm.v v24,0(a1) add sp,sp,t1 jr ra There are 2 issues here: First, 2 vlm.v mask loads are missing which is incorrect code-gen. Second, the code quality is bad which is the duplicate bug filed here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
next reply other threads:[~2023-02-03 8:20 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-03 8:20 juzhe.zhong at rivai dot ai [this message] 2023-03-07 13:45 ` [Bug target/108654] " cvs-commit at gcc dot gnu.org 2023-03-23 8:40 ` cvs-commit at gcc dot gnu.org 2023-03-25 2:31 ` juzhe.zhong at rivai dot ai 2023-03-25 2:32 ` juzhe.zhong at rivai dot ai
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