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From: "palmer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/108826] Inefficient address generation on POWER and RISC-V Date: Thu, 16 Feb 2023 18:21:10 +0000 [thread overview] Message-ID: <bug-108826-4-nqr3FJvyzv@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-108826-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108826 --- Comment #5 from palmer at gcc dot gnu.org --- We've run into a handful of things that look like this before, I'm not sure if it's a backend issue or something more general. There's two patterns here that are frequently bad on RISC-V: "unsigned int" array indices and unsigned int shifting. I think they might both boil down to some problems we have tracking the high parts of registers around ABI boundaries. FWIW, the smallest bad code I can get is unsigned int func(unsigned int ui) { return (ui >> 6 & 5) << 2; } func: srliw a0,a0,6 slliw a0,a0,2 andi a0,a0,20 ret which is particularly awkward as enough is going right to try and move that andi, but we still end up with the double shifts.
next prev parent reply other threads:[~2023-02-16 18:21 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-16 17:53 [Bug rtl-optimization/108826] New: " tkoenig at gcc dot gnu.org 2023-02-16 17:56 ` [Bug rtl-optimization/108826] " pinskia at gcc dot gnu.org 2023-02-16 18:00 ` pinskia at gcc dot gnu.org 2023-02-16 18:00 ` pinskia at gcc dot gnu.org 2023-02-16 18:09 ` pinskia at gcc dot gnu.org 2023-02-16 18:21 ` palmer at gcc dot gnu.org [this message] 2023-02-16 18:25 ` pinskia at gcc dot gnu.org 2023-09-28 19:55 ` pinskia at gcc dot gnu.org
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