[Bug rtl-optimization/109079] Missing optimization for x86 avx intrinsic _mm256_zeroall().

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109079

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|target                      |rtl-optimization

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #1)
> I think it wasn't intended to be used this way, but sure.  Currently it's a
> black-box in the target I think and so nothing sees the redundancy.

_mm256_zeroall is emitted as:

(insn 6 3 7 2 (parallel [
            (unspec_volatile [
                    (const_int 0 [0])
                ] UNSPECV_VZEROALL)
            (set (reg:V8SI 20 xmm0)
                (const_vector:V8SI [
                        (const_int 0 [0]) repeated x8
                    ]))
            (set (reg:V8SI 21 xmm1)
                (const_vector:V8SI [
                        (const_int 0 [0]) repeated x8
                    ]))
...
            (set (reg:V8SI 51 xmm15)
                (const_vector:V8SI [
                        (const_int 0 [0]) repeated x8
                    ]))
        ])

and _mm256_setzero_ps as:

(insn 7 6 8 2 (set (reg:V8SF 83)
        (const_vector:V8SF [
                (const_double:SF 0.0 [0x0.0p+0]) repeated x8
            ]))

There is mode mismatch between (insn 6) and (insn 7) so postreload CSE is not
able to eliminate (insn 7).

Using the following patch^w hack that changes the mode of vzeroall registers:

--cut here--
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index b4d9ab40ab9..cf15ca8f611 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1737,9 +1737,9 @@ (define_predicate "vzeroall_operation"

       if (GET_CODE (elt) != SET
          || GET_CODE (SET_DEST (elt)) != REG
-         || GET_MODE (SET_DEST (elt)) != V8SImode
+         || GET_MODE (SET_DEST (elt)) != V8SFmode
          || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
-         || SET_SRC (elt) != CONST0_RTX (V8SImode))
+         || SET_SRC (elt) != CONST0_RTX (V8SFmode))
        return false;
     }
   return true;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 172ec3bea4f..81e02086606 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -25244,8 +25244,8 @@ (define_expand "avx_vzeroall"

   for (regno = 0; regno < nregs; regno++)
     XVECEXP (operands[0], 0, regno + 1)
-      = gen_rtx_SET (gen_rtx_REG (V8SImode, GET_SSE_REGNO (regno)),
-                    CONST0_RTX (V8SImode));
+      = gen_rtx_SET (gen_rtx_REG (V8SFmode, GET_SSE_REGNO (regno)),
+                    CONST0_RTX (V8SFmode));
 })

 (define_insn "*avx_vzeroall"
--cut here--

the compiler is able to eliminate (insn 7) in postreload pass, producing:

fn:
        vzeroall
        vmovups %ymm0, (%rdi)
        vzeroupper
        ret

It looks to me that postreload CSE should be taught about the equivalence of
vector modes - a V8SFmode zero has the same bit representation as V8SImode zero
(and V4DImode, ...), as long as the mode size is the same.

Recategorizing as rtl-optimization.