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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64
Date: Mon, 13 Mar 2023 17:01:37 +0000	[thread overview]
Message-ID: <bug-109092-4-8tLvfuN57a@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-109092-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |law at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
In this case that would be certainly better, because if the intent is to never
match for 
move from vl register, then even subreg of vl would be a vl register and so if
it punted just on moves from vl REG and not SUBREG thereof, after reload it
could get vl REG from the SUBREG and fail at that point.
Note, *zero_extendsidi2_internal uses the #c1 way...

  parent reply	other threads:[~2023-03-13 17:01 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-10 17:32 [Bug rtl-optimization/109092] New: " zsojka at seznam dot cz
2023-03-10 17:37 ` [Bug target/109092] " pinskia at gcc dot gnu.org
2023-03-13  8:52 ` rguenth at gcc dot gnu.org
2023-03-13 10:03 ` ubizjak at gmail dot com
2023-03-13 17:01 ` jakub at gcc dot gnu.org [this message]
2023-03-14 18:12 ` law at gcc dot gnu.org
2023-03-14 18:30 ` ubizjak at gmail dot com
2023-03-15  1:53 ` juzhe.zhong at rivai dot ai
2023-03-17  9:50 ` cvs-commit at gcc dot gnu.org
2023-03-27  7:44 ` pinskia at gcc dot gnu.org
2024-01-22 12:55 ` cvs-commit at gcc dot gnu.org

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