[Bug target/109117] New: "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[Bug target/109117] New: "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[lin1.hu at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

            Bug ID: 109117
           Summary: "__builtin_ia32_vaesdec_v16qi" compiled only with
                    option -mvaes report ICE.
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lin1.hu at intel dot com
  Target Milestone: ---

When the compiler compiles "__builtin_ia32_vaesdec_v16qi" with option
-mvaes,-no-avx512vl, it reports ICE.

The detail can refer to https://godbolt.org/z/fEGavbGWz.

Test-case:

typedef char __v16qi __attribute__ ((__vector_size__(16)));
typedef long long __m128i __attribute__((__vector_size__(16),
__aligned__(16)));
volatile __v16qi x, y;
volatile __m128i res;

void
foo (void)
{
    res = (__m128i) __builtin_ia32_vaesdec_v16qi (x, y);
}

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[lin1.hu at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

--- Comment #1 from lin1.hu at intel dot com ---
Created attachment 54657
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54657&action=edit
Untested fix.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[lin1.hu at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

--- Comment #2 from lin1.hu at intel dot com ---
Created attachment 54659
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54659&action=edit
No need AVX512VL for 256bit, so I modify the original patch.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[lin1.hu at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

lin1.hu at intel dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
  Attachment #54659|No need AVX512VL for        |0001-i386-Add-missing-OPTIO
        description|256bit, so I modify the     |N_MASK_ISA_AVX512VL-in-i386
                   |original patch.             |-bu.patch

--- Comment #3 from lin1.hu at intel dot com ---
Comment on attachment 54659
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54659
0001-i386-Add-missing-OPTION_MASK_ISA_AVX512VL-in-i386-bu.patch

No need AVX512VL for 256bit, so I modify the original patch.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[lin1.hu at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

--- Comment #4 from lin1.hu at intel dot com ---
(In reply to lin1.hu from comment #2)
> Created attachment 54659 [details]
> 0001-i386-Add-missing-OPTION_MASK_ISA_AVX512VL-in-i386-bu.patch

Regtested on x86_64-pc-linux-gnu.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:a9ae16db8cbb2c0ec8e8384ac38ce618f9af1e3a

commit r13-6680-ga9ae16db8cbb2c0ec8e8384ac38ce618f9af1e3a
Author: Hu, Lin1 <lin1.hu@intel.com>
Date:   Mon Mar 13 15:50:11 2023 +0800

    i386:Add missing OPTION_MASK_ISA_AVX512VL in i386-builtin.def for VAES
builtins

    gcc/ChangeLog:

            PR target/109117
            * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
            __builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
            __builtin_ia32_vaesenclast_v16qi): Require
OPTION_MASK_ISA_AVX512VL.

    gcc/testsuite/ChangeLog:

            PR target/109117
            * gcc.target/i386/pr109117-1.c: New test.