[Bug c/109272] New: RISCV: vbool*_t better opportunities of code generation

[Bug c/109272] New: RISCV: vbool*_t better opportunities of code generation

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109272

            Bug ID: 109272
           Summary: RISCV: vbool*_t better opportunities of code
                    generation
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Assume we have sample code as below.
#include "riscv_vector.h"

void
test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
    vbool8_t v1 = *(vbool8_t*)in;
    vbool16_t v2 = *(vbool16_t*)in;

    *(vbool8_t*)(out + 100) = v1;
    *(vbool16_t*)(out + 200) = v2;
}

It will generate the assembly code like

test_vbool8_then_vbool16:
        csrr    t0,vlenb
        slli    t1,t0,1
        csrr    a3,vlenb
        sub     sp,sp,t1
        csrr    a5,vlenb
        slli    a3,a3,1
        add     a3,a3,sp
        addi    a2,a1,100
        srli    a5,a5,3
        vsetvli a4,zero,e8,m1,ta,ma
        sub     a5,a3,a5
        vlm.v   v24,0(a0)
        vsm.v   v24,0(a2)
        vsm.v   v24,0(a5)
        addi    a1,a1,200
        csrr    t0,vlenb
        vsetvli a3,zero,e8,mf2,ta,ma
        slli    t1,t0,1
        vlm.v   v24,0(a5)
        vsm.v   v24,0(a1)
        add     sp,sp,t1
        jr      ra

Actually we can optimize the generated code to:

test_vbool8_then_vbool4:
        addi    a3,a1,100
        vsetvli a4,zero,e8,m1,ta,ma
        addi    a1,a1,200
        vlm.v   v24,0(a0)
        vsm.v   v24,0(a3)
        vsetvli a3,zero,e8,mf2,ta,ma
        vlm.v   v24,0(a0)
        vsm.v   v24,0(a1)
        ret

[Bug target/109272] RISCV: vbool*_t opportunities of a better code generation

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109272

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:a8d5e14f524283484c2a466353f92f7eaadae9f7

commit r14-235-ga8d5e14f524283484c2a466353f92f7eaadae9f7
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Apr 25 22:29:04 2023 +0800

    RISC-V: Bugfix for RVV vbool*_t vn_reference_equal

    In most architecture the precision_size of vbool*_t types are caculated
    like as the multiple of the type size.  For example:
    precision_size = type_size * 8 (aka, bit count per bytes).

    Unfortunately, some architecture like RISC-V will adjust the
    precision_size
    for the vbool*_t in order to align the ISA. For example as below.
    type_size      = [1, 1, 1, 1,  2,  4,  8]
    precision_size = [1, 2, 4, 8, 16, 32, 64]

    Then the precision_size of RISC-V vbool*_t will not be the multiple of
    the
    type_size. This PATCH try to enrich this case when comparing the
    vn_reference.

    Given we have the below code:
    void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict
    out) {
        vbool8_t v1 = *(vbool8_t*)in;
        vbool16_t v2 = *(vbool16_t*)in;

        *(vbool8_t*)(out + 100) = v1;
        *(vbool16_t*)(out + 200) = v2;
    }

    Before this PATCH:
    csrr    t0,vlenb
    slli    t1,t0,1
    csrr    a3,vlenb
    sub     sp,sp,t1
    slli    a4,a3,1
    add     a4,a4,sp
    addi    a2,a1,100
    vsetvli a5,zero,e8,m1,ta,ma
    sub     a3,a4,a3
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a2)
    vsm.v   v24,0(a3)
    addi    a1,a1,200
    csrr    t0,vlenb
    vsetvli a4,zero,e8,mf2,ta,ma
    slli    t1,t0,1
    vlm.v   v24,0(a3)
    vsm.v   v24,0(a1)
    add     sp,sp,t1
    jr      ra

    After this PATCH:
    addi    a3,a1,100
    vsetvli a4,zero,e8,m1,ta,ma
    addi    a1,a1,200
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a3)
    vsetvli a5,zero,e8,mf2,ta,ma
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a1)
    ret

            PR target/109272

    gcc/ChangeLog:

            * tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
            check for vn_reference equal.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr108185-4.c: Update test check
            condition.
            * gcc.target/riscv/rvv/base/pr108185-5.c: Likewise.
            * gcc.target/riscv/rvv/base/pr108185-6.c: Likewise.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/109272] RISCV: vbool*_t opportunities of a better code generation

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109272

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from Kito Cheng <kito at gcc dot gnu.org> ---
Fixed on trunk