[Bug middle-end/109347] New: [lra] Spill failure for architecture without CC

[Bug middle-end/109347] New: [lra] Spill failure for architecture without CC

[piggynl at outlook dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

            Bug ID: 109347
           Summary: [lra] Spill failure for architecture without CC
           Product: gcc
           Version: 12.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: piggynl at outlook dot com
  Target Milestone: ---

Created attachment 54791
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54791&action=edit
Reproduce for riscv64

For all architectures without condition code, when all registers are in use,
gcc fails to perform a spill.

mips64 and riscv64 are failing with certain code. 

For example, the codes for mips64 and riscv64 reproducing the bug are in
attachments.

The expected behavior is generating a spill asm sequence before the `if` block
and a restore sequence after, so it will be a free register in the `if` block.

gcc is failing an assertion error with the examples. With a release build, gcc
falls into an infinity loop.

The assertion fails in lra.c:

            if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun))
              {
                /* We already made the edge no-critical in ira.c::ira */
                lra_assert (!EDGE_CRITICAL_P (e));
                ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                rtx_insn *tmp = BB_HEAD (e->dest);
                if (LABEL_P (tmp))

The assertion was introduced in e3b3b59683c1.

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[piggynl at outlook dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #1 from Piggy NL <piggynl at outlook dot com> ---
Created attachment 54792
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54792&action=edit
Reproduce for mips64

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Piggy NL from comment #0)
> The assertion was introduced in e3b3b59683c1.

r11-5002-ge3b3b59683c1e7

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
On the trunk I get:
t.c: In function ‘f’:
t.c:94:1: error: s0 cannot be used in ‘asm’ here
   94 | }
      | ^

First with the RISCV example.
After removing the s0 variable usage I still get the ICE.

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 54793
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54793&action=edit
Fixed up riscv64 testcase

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 54794
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54794&action=edit
testcase for riscv32-elf

Here is a testcase which also fails for riscv32-elf. Note it only fails at -O0.

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Oh if we add back the s0 case, it fails at -O1 and above too.

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
  Attachment #54791|0                           |1
        is obsolete|                            |
  Attachment #54793|0                           |1
        is obsolete|                            |
  Attachment #54794|0                           |1
        is obsolete|                            |

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 54795
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54795&action=edit
testcase for riscv64-elf and riscv32-elf

This is new testcase fails for both riscv32 and riscv64 at -O0 and -O1.
disabling s0 for -O0 too.

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Target|                            |riscv32-elf, riscv64-elf,
                   |                            |mips64-eabi
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2023-03-30

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |7.3.0

--- Comment #8 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
MIPS64 fails even for GCC 7:
t.c: In function ‘f’:
t.c:91:1: error: unable to find a register to spill
 }
 ^
t.c:91:1: error: this is the insn:
(insn 36 73 72 2 (set (reg:DI 200 [198])
        (plus:DI (reg:DI 201 [orig:194 t9.0_1 ] [194])
            (const_int 1 [0x1]))) "t.c":60 14 {*adddi3}
     (expr_list:REG_DEAD (reg:DI 201 [orig:194 t9.0_1 ] [194])
        (nil)))
t.c:91:1: internal compiler error: in assign_by_spills, at lra-assigns.c:1476

[Bug middle-end/109347] [lra] Spill failure for architecture without CC

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Even for pre-LRA with reload in GCC 4.7.0:
t.c: In function ‘f’:
t.c:91:1: note: unable to find a register to spill in class ‘GR_REGS’
t.c:91:1: note: this is the insn:
(insn 33 32 34 2 (set (reg:DI 198)
        (plus:DI (reg:DI 194 [ t9.0 ])
            (const_int 1 [0x1]))) t.c:60 11 {*adddi3}
     (expr_list:REG_DEAD (reg:DI 194 [ t9.0 ])
        (nil)))
t.c:91:1: internal compiler error: in spill_failure, at reload1.c:2120
unrecognized DWARF version in .debug_info at 6
0x70e2bf _fatal_insn
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/rtl-error.c:106
0x705bab spill_failure
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/reload1.c:2120
0x705bab find_reload_regs
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/reload1.c:2046
0x705bab select_reload_regs
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/reload1.c:2066
0x705bab reload
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/reload1.c:993
0x65fe6e do_reload
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/ira.c:3733
0x65fe6e rest_of_handle_reload
        /bajas/pinskia/src/toolchain-47/scripts/../src/gcc/ira.c:3824
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.

So I am sure this is almost not a regression.