[Bug rtl-optimization/109416] New: Missed constant propagation cases after reload

[Bug rtl-optimization/109416] New: Missed constant propagation cases after reload

[sinan.lin at linux dot alibaba.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416

            Bug ID: 109416
           Summary: Missed constant propagation cases after reload
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sinan.lin at linux dot alibaba.com
  Target Milestone: ---

gcc splits a movdi_32bit pattern into two insns after reload in rv32, which
brings constant propagation opportunities.

e.g.
```
long long int Data;

void init() {
    Data = 0x0;
}

void init2() {
    Data = 0xf00000000;
}

void init3() {
    Data = 0xf0000000f;
}

```


asm output
```
init:
        lui     a5,%hi(Data)
        li      a3,0
        li      a4,0
        sw      a3,%lo(Data)(a5)
        sw      a4,%lo(Data+4)(a5)
        ret
init2:
        lui     a5,%hi(Data)
        li      a2,0
        li      a3,15
        sw      a2,%lo(Data)(a5)
        sw      a3,%lo(Data+4)(a5)
        ret
init3:
        lui     a5,%hi(Data)
        li      a2,15
        li      a3,15
        sw      a2,%lo(Data)(a5)
        sw      a3,%lo(Data+4)(a5)
        ret
```

could be optimized into
```
init:
        lui     a5,%hi(Data)
        sw      zero,%lo(Data)(a5)
        sw      zero,%lo(Data+4)(a5)
        ret
init2:
        lui     a5,%hi(Data)
        li      a2,15
        sw      zero,%lo(Data)(a5)
        sw      a2,%lo(Data+4)(a5)
        ret
init3:
        lui     a5,%hi(Data)
        li      a2,15
        sw      a2,%lo(Data)(a5)
        sw      a2,%lo(Data+4)(a5)
        ret
```



A similar case in AArch64
```
__int128 Data;

void init() {
    Data = 0xfffff;
}
```

output
```
init:
        adrp    x0, .LANCHOR0
        add     x0, x0, :lo12:.LANCHOR0
        mov     x2, 1048575
        mov     x3, 0
        stp     x2, x3, [x0]
        ret
```
could be optimized into

```
init:
        adrp    x0, .LANCHOR0
        add     x0, x0, :lo12:.LANCHOR0
        mov     x2, 1048575
        stp     x2, xzr, [x0]
        ret
```

[Bug rtl-optimization/109416] Missed constant propagation cases after reload

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Note aarch64 issue is totally different:

(insn 13 6 14 2 (set (reg:DI 2 x2 [94])
        (const_int 1048575 [0xfffff])) "/app/example.cpp":5:10 65
{*movdi_aarch64}
     (nil))
(insn 14 13 8 2 (set (reg:DI 3 x3 [+8 ])
        (const_int 0 [0])) "/app/example.cpp":5:10 65 {*movdi_aarch64}
     (nil))
(insn 8 14 11 2 (set (mem/c:TI (reg/f:DI 0 x0 [92]) [1 Data+0 S16 A128])
        (reg:TI 2 x2 [94])) "/app/example.cpp":5:10 70 {*movti_aarch64}
     (nil))

Please file that seperately.

[Bug target/109416] Missed constant propagation cases after reload

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2023-04-05
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
For the init function:
(insn 5 2 6 (set (reg/f:SI 15 a5 [134])
        (high:SI (symbol_ref:SI ("Data") [flags 0x86]  <var_decl 0x7f183060d900
Data>))) "t4.c":5:10 180 {*movsi_internal}
     (expr_list:REG_EQUIV (high:SI (symbol_ref:SI ("Data") [flags 0x86] 
<var_decl 0x7f183060d900 Data>))
        (nil)))
(insn 6 5 13 (set (reg/f:SI 15 a5 [135])
        (lo_sum:SI (reg/f:SI 15 a5 [134])
            (symbol_ref:SI ("Data") [flags 0x86]  <var_decl 0x7f183060d900
Data>))) "t4.c":5:10 174 {*lowsi}
     (expr_list:REG_EQUIV (symbol_ref:SI ("Data") [flags 0x86]  <var_decl
0x7f183060d900 Data>)
        (nil)))
(insn 13 6 14 (set (reg:SI 13 a3 [137])
        (const_int 0 [0])) "t4.c":5:10 180 {*movsi_internal}
     (nil))
(insn 14 13 15 (set (reg:SI 14 a4 [+4 ])
        (const_int 0 [0])) "t4.c":5:10 180 {*movsi_internal}
     (nil))
(insn 15 14 16 (set (mem/c:SI (reg/f:SI 15 a5 [135]) [1 Data+0 S4 A64])
        (reg:SI 13 a3 [137])) "t4.c":5:10 180 {*movsi_internal}
     (expr_list:REG_DEAD (reg:SI 13 a3 [137])
        (nil)))
(insn 16 15 23 (set (mem/c:SI (plus:SI (reg/f:SI 15 a5 [135])
                (const_int 4 [0x4])) [1 Data+4 S4 A32])
        (reg:SI 14 a4 [+4 ])) "t4.c":5:10 180 {*movsi_internal}
     (expr_list:REG_DEAD (reg/f:SI 15 a5 [135])
        (expr_list:REG_DEAD (reg:SI 14 a4 [+4 ])
            (nil))))


LRA/reload decides to change:
(insn 7 6 10 2 (set (mem/c:DI (reg/f:SI 135) [1 Data+0 S8 A64])
        (const_int 0 [0])) "t4.c":5:10 178 {*movdi_32bit}
     (expr_list:REG_DEAD (reg/f:SI 135)
        (nil)))

To:
(insn 7 6 12 2 (set (reg:DI 13 a3 [137])
        (const_int 0 [0])) "t4.c":5:10 178 {*movdi_32bit}
     (nil))
(insn 12 7 10 2 (set (mem/c:DI (reg/f:SI 15 a5 [135]) [1 Data+0 S8 A64])
        (reg:DI 13 a3 [137])) "t4.c":5:10 178 {*movdi_32bit}
     (nil))

I would have expected not have happened ...
So the init function is definitely a target issue As LRA should have kept it as
one store instruction ...

[Bug target/109416] Missed constant propagation cases after reload

[sinan.lin at linux dot alibaba.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416

--- Comment #3 from Sinan <sinan.lin at linux dot alibaba.com> ---
Hi Andrew,

Thank you for taking the time to explain the issue. I appreciate it.

I think the issue between init/init2 and init3 might be different. Regarding
init3, any 32-bit backend attempting to split a complex constant will encounter
such a suboptimal case.

I tried with mip in gcc 12, and here are the ouputs for `init` and `init3`

init:
        lui     $2,%hi(Data)
        move    $5,$0
        move    $4,$0
        sw      $5,%lo(Data+4)($2)
        jr      $31
        sw      $4,%lo(Data)($2)

init3:
        lui     $2,%hi(Data)
        li      $5,15                 # 0xf
        li      $4,15                 # 0xf
        sw      $5,%lo(Data+4)($2)
        jr      $31
        sw      $4,%lo(Data)($2)

register $4 or $5 could be eliminated.