[Bug target/109657] (a ? -1 : 0) | b could be optimized better for aarch64

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109657

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Andrew Pinski <pinskia@gcc.gnu.org>:

https://gcc.gnu.org/g:7cc33d12dca84befde69259a17fab8224e2e4025

commit r14-412-g7cc33d12dca84befde69259a17fab8224e2e4025
Author: Andrew Pinski <apinski@marvell.com>
Date:   Fri Apr 28 05:22:34 2023 +0000

    target: [PR109657] (a ? -1 : 0) | b could be optimized better for aarch64

    There is no canonical form for this case defined. So the aarch64 backend
needs
    a pattern to match both of these forms.

    The forms are:
    (set (reg/i:SI 0 x0)
        (if_then_else:SI (eq (reg:CC 66 cc)
                (const_int 0 [0]))
            (reg:SI 97)
            (const_int -1 [0xffffffffffffffff])))
    and
    (set (reg/i:SI 0 x0)
        (ior:SI (neg:SI (ne:SI (reg:CC 66 cc)
                    (const_int 0 [0])))
            (reg:SI 102)))

    Currently the aarch64 backend matches the first form so this
    patch adds a insn_and_split to match the second form and
    convert it to the first form.

    OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions

            PR target/109657

    gcc/ChangeLog:

            * config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
            insn_and_split pattern.

    gcc/testsuite/ChangeLog:

            * gcc.target/aarch64/csinv-2.c: New test.