[Bug c/109687] New: riscv64-unknown-elf-gcc internal error on embench when using bit manipulation extensions

[Bug c/109687] New: riscv64-unknown-elf-gcc internal error on embench when using bit manipulation extensions

[david_harris at hmc dot edu]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109687

            Bug ID: 109687
           Summary: riscv64-unknown-elf-gcc internal error on embench when
                    using bit manipulation extensions
           Product: gcc
           Version: 12.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: david_harris at hmc dot edu
  Target Milestone: ---

Created attachment 54965
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54965&action=edit
-freport-bug output

This bug occurs when march=rv32imac_zba_zbb_zbs
but not when march=rv32imac

riscv64-unknown-elf-gcc -c -fdata-sections -ffunction-sections
-march=rv32imac_zba_zbb_zbs -mabi=ilp32 -Os -msave-restore
-I/home/harris/cvw/addins/embench-iot/support
-I/home/harris/cvw/addins/embench-iot/config/riscv32/boards/rv32wallyverilog
-I/home/harris/cvw/addins/embench-iot/config/riscv32/chips/generic
-I/home/harris/cvw/addins/embench-iot/config/riscv32 -DCPU_MHZ=1
-DWARMUP_HEAT=1 -o libminver.o
/home/harris/cvw/addins/embench-iot/src/minver/libminver.c

/home/harris/cvw/addins/embench-iot/src/minver/libminver.c: In function
'minver.part.0':
/home/harris/cvw/addins/embench-iot/src/minver/libminver.c:211:1: error:
unrecognizable insn:
  211 | }
      | ^
(insn 435 0 0 (set (reg:SI 275)
        (const_int 2048 [0x800])) -1
     (expr_list:REG_EQUAL (const_int 2048 [0x800])
        (nil)))
during RTL pass: reload
/home/harris/cvw/addins/embench-iot/src/minver/libminver.c:211:1: internal
compiler error: in extract_insn, at recog.cc:2791
0x619df0 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/rtl-error.cc:108
0x619e12 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/rtl-error.cc:116
0x6192dc extract_insn(rtx_insn*)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/recog.cc:2791
0x9fe384 ira_remove_insn_scratches(rtx_insn*, bool, _IO_FILE*, rtx_def*
(*)(rtx_def*))
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/ira.cc:5356
0xa39509 remove_insn_scratches
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/lra.cc:2091
0xa3ae47 lra_emit_move(rtx_def*, rtx_def*)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/lra.cc:512
0xa4e49d curr_insn_transform
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/lra-constraints.cc:4608
0xa4fc54 lra_constraints(bool)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/lra-constraints.cc:5203
0xa3d8d2 lra(_IO_FILE*)
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/lra.cc:2375
0x9f86d9 do_reload
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/ira.cc:5940
0x9f86d9 execute
        /opt/riscv/riscv-gnu-toolchain/gcc/gcc/ira.cc:6126
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

[Bug c/109687] riscv64-unknown-elf-gcc internal error on embench when using bit manipulation extensions

[david_harris at hmc dot edu]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109687

--- Comment #1 from David Harris <david_harris at hmc dot edu> ---
harris@vlsi:~/cvw/benchmarks/embench$ riscv64-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=riscv64-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/opt/riscv/libexec/gcc/riscv64-unknown-elf/12.2.0/lto-wrapper
Target: riscv64-unknown-elf
Configured with: /opt/riscv/riscv-gnu-toolchain/gcc/configure
--target=riscv64-unknown-elf --prefix=/opt/riscv --disable-shared
--disable-threads --enable-languages=c,c++ --with-pkgversion=
--with-system-zlib --enable-tls --with-newlib
--with-sysroot=/opt/riscv/riscv64-unknown-elf
--with-native-system-header-dir=/include --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libgomp --disable-nls
--disable-tm-clone-registry --src=/opt/riscv/riscv-gnu-toolchain/gcc
--enable-multilib
--with-multilib-generator='rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;'
--with-abi=lp64d --with-arch=rv64imafdc --with-tune=rocket --with-isa-spec=2.2
'CFLAGS_FOR_TARGET=-Os   -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os  
-mcmodel=medlow'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 12.2.0 ()

[Bug target/109687] riscv64-unknown-elf-gcc internal error on embench when using bit manipulation extensions

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109687

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|riscv64-elf                 |riscv32-elf
         Resolution|---                         |DUPLICATE
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Already fixed for GCC 13.1.0

*** This bug has been marked as a duplicate of bug 106532 ***