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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
Date: Fri, 24 Nov 2023 11:59:42 +0000 [thread overview]
Message-ID: <bug-109977-4-5ItzjkDvfo@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-109977-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |jakub at gcc dot gnu.org
--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I agree with the analysis and
2023-11-24 Andrew Pinski <pinskia@gmail.com>
Jakub Jelinek <jakub@redhat.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
rather than %<vw> for alternative with r constraint on input operand.
* gcc.dg/pr109977.c: New test.
--- gcc/config/aarch64/aarch64-simd.md.jj 2023-11-22 22:55:20.577075762
+0100
+++ gcc/config/aarch64/aarch64-simd.md 2023-11-24 12:51:22.855215700 +0100
@@ -269,7 +269,7 @@ (define_insn "aarch64_simd_stp<mode>"
"TARGET_SIMD"
{@ [ cons: =0 , 1 ; attrs: type ]
[ Umn , w ; neon_stp ] stp\t%<Vetype>1, %<Vetype>1,
%y0
- [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vw>1, %<vw>1, %y0
+ [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vwcore>1, %<vwcore>1,
%y0
}
)
--- gcc/testsuite/gcc.dg/pr109977.c.jj 2023-11-24 12:51:04.551473591 +0100
+++ gcc/testsuite/gcc.dg/pr109977.c 2023-11-24 12:50:44.158760916 +0100
@@ -0,0 +1,16 @@
+/* PR target/109977 */
+/* { dg-do compile } */
+/* { dg-options "-Og" } */
+
+typedef double __attribute__((__vector_size__ (8))) V;
+typedef double __attribute__((__vector_size__ (16))) W;
+V v;
+int i;
+extern void bar (void *);
+
+void
+foo (void)
+{
+ W w = __builtin_shufflevector (v, (W) { }, 0, 0);
+ bar (&w);
+}
fixes it (though it will take me a while to find where to bootstrap/regtest
this).
next prev parent reply other threads:[~2023-11-24 11:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 5:14 [Bug target/109977] New: " zsojka at seznam dot cz
2023-05-26 5:30 ` [Bug target/109977] " pinskia at gcc dot gnu.org
2023-05-26 5:31 ` pinskia at gcc dot gnu.org
2023-08-02 20:48 ` pinskia at gcc dot gnu.org
2023-10-17 10:35 ` rguenth at gcc dot gnu.org
2023-11-24 11:59 ` jakub at gcc dot gnu.org [this message]
2023-11-24 12:03 ` [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5 sjames at gcc dot gnu.org
2023-11-25 9:31 ` cvs-commit at gcc dot gnu.org
2023-11-25 9:33 ` jakub at gcc dot gnu.org
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