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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
Date: Fri, 26 May 2023 05:30:43 +0000 [thread overview]
Message-ID: <bug-109977-4-xAYEitMOSe@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-109977-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |14.0
Host|x86_64-pc-linux-gnu |
Last reconfirmed| |2023-05-26
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(insn 12 11 13 (set (mem/c:V2DF (plus:DI (reg/f:DI 31 sp)
(const_int 16 [0x10])) [1 w+0 S16 A128])
(vec_duplicate:V2DF (reg:DF 0 x0 [orig:95 v ] [95])))
"/app/example.cpp":12:5 1392 {aarch64_simd_stpv2df}
(expr_list:REG_DEAD (reg:DF 0 x0 [orig:95 v ] [95])
(nil)))
(define_insn "aarch64_simd_stp<mode>"
[(set (match_operand:VP_2E 0 "aarch64_mem_pair_lanes_operand" "=Umn,Umn")
(vec_duplicate:VP_2E (match_operand:<VEL> 1 "register_operand"
"w,r")))]
"TARGET_SIMD"
"@
stp\\t%<Vetype>1, %<Vetype>1, %y0
stp\\t%<vw>1, %<vw>1, %y0"
[(set_attr "type" "neon_stp, store_<ldpstp_vel_sz>")]
)
;; For scalar usage of vector/FP registers, widening
(define_mode_attr vw [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V2SF "s") (V4SF "s")
(V2DF "d")])
Most likely should be using vwcore instead:
;; Corresponding core element mode for each vector mode. This is a
;; variation on <vw> mapping FP modes to GP regs.
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V4HF "w") (V8HF "w")
(V4BF "w") (V8BF "w")
(V2SF "w") (V4SF "w")
(V2DF "x")
(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
(VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
(VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
(VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
(VNx4SI "w") (VNx2SI "w")
(VNx4SF "w") (VNx2SF "w")
(VNx2DI "x")
(VNx2DF "x")])
next prev parent reply other threads:[~2023-05-26 5:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 5:14 [Bug target/109977] New: " zsojka at seznam dot cz
2023-05-26 5:30 ` pinskia at gcc dot gnu.org [this message]
2023-05-26 5:31 ` [Bug target/109977] " pinskia at gcc dot gnu.org
2023-08-02 20:48 ` pinskia at gcc dot gnu.org
2023-10-17 10:35 ` rguenth at gcc dot gnu.org
2023-11-24 11:59 ` jakub at gcc dot gnu.org
2023-11-24 12:03 ` [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5 sjames at gcc dot gnu.org
2023-11-25 9:31 ` cvs-commit at gcc dot gnu.org
2023-11-25 9:33 ` jakub at gcc dot gnu.org
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