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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/110701] [14 Regression] Wrong code at -O1/2/3/s on x86_64-linux-gnu
Date: Wed, 04 Oct 2023 16:12:06 +0000	[thread overview]
Message-ID: <bug-110701-4-8XoQAhwOZW@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110701-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110701

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:263369b2f7f726a3d4b269678d2c13a9d06a041e

commit r14-4398-g263369b2f7f726a3d4b269678d2c13a9d06a041e
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Wed Oct 4 17:11:23 2023 +0100

    PR rtl-optimization/110701: Fix SUBREG SET_DEST handling in combine.

    This patch is my proposed fix to PR rtl-optimization 110701, a latent bug
    in combine's record_dead_and_set_regs_1 exposed by recent improvements to
    simplify_subreg.

    The issue involves the handling of (normal) SUBREG SET_DESTs as in the
    instruction:

            (set (subreg:HI (reg:SI x) 0) (expr:HI y))

    The semantics of this are that the bits specified by the SUBREG are set
    to the SET_SRC, y, and that the other bits of the SET_DEST are left/become
    undefined.  To simplify explanation, we'll only consider lowpart SUBREGs
    (though in theory non-lowpart SUBREGS could be handled), and the fact that
    bits outside of the lowpart WORD retain their original values (treating
    these as undefined is a missed optimization rather than incorrect code
    bug, that only affects targets with less than 64-bit words).

    The bug is that combine simulates the behaviour of the above instruction,
    for calculating nonzero_bits and set_sign_bit_copies, in the function
    record_value_for_reg, by using the equivalent of:

            (set (reg:SI x) (subreg:SI (expr:HI y))

    by calling gen_lowpart on the SET_SRC.  Alas, the semantics of this
    revised instruction aren't always equivalent to the original.

    In the test case for PR110701, the original instruction

            (set (subreg:HI (reg:SI x), 0)
                 (and:HI (subreg:HI (reg:SI y) 0)
                         (const_int 340)))

    which (by definition) leaves the top bits of x undefined, is mistakenly
    considered to be equivalent to

            (set (reg:SI x) (and:SI (reg:SI y) (const_int 340)))

    where gen_lowpart's freedom to do anything with paradoxical SUBREG bits,
    has now cleared the high bits.  The same bug also triggers when the
    SET_SRC is say (subreg:HI (reg:DI z)), where gen_lowpart transforms
    this into (subreg:SI (reg:DI z)) which defines bits 16-31 to be the
    same as bits 16-31 of z.

    The fix is that after calling record_value_for_reg, we need to mark
    the bits that should be undefined as undefined, in case gen_lowpart,
    which performs transforms appropriate for r-values, has changed the
    interpretation of the SUBREG when used as an l-value.

    2023-10-04  Roger Sayle  <roger@nextmovesoftware.com>

    gcc/ChangeLog
            PR rtl-optimization/110701
            * combine.cc (record_dead_and_set_regs_1): Split comment into
            pieces placed before the relevant clauses.  When the SET_DEST
            is a partial_subreg_p, mark the bits outside of the updated
            portion of the destination as undefined.

    gcc/testsuite/ChangeLog
            PR rtl-optimization/110701
            * gcc.target/i386/pr110701.c: New test case.

  parent reply	other threads:[~2023-10-04 16:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-17 10:21 [Bug c/110701] New: " shaohua.li at inf dot ethz.ch
2023-07-17 12:43 ` [Bug rtl-optimization/110701] [14 Regression] " xry111 at gcc dot gnu.org
2023-07-17 17:51 ` pinskia at gcc dot gnu.org
2023-07-17 17:55 ` pinskia at gcc dot gnu.org
2023-07-17 17:58 ` pinskia at gcc dot gnu.org
2023-07-18 15:38 ` roger at nextmovesoftware dot com
2023-07-18 17:17 ` roger at nextmovesoftware dot com
2023-07-27 18:23 ` roger at nextmovesoftware dot com
2023-10-04 16:12 ` cvs-commit at gcc dot gnu.org [this message]
2023-10-11  7:59 ` roger at nextmovesoftware dot com

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