[Bug middle-end/110950] New: RISC-V vector ICE in expand_const_vector

[Bug middle-end/110950] New: RISC-V vector ICE in expand_const_vector

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

            Bug ID: 110950
           Summary: RISC-V vector ICE in expand_const_vector
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55708
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55708&action=edit
C source

The following code (testcase.c) causes an ICE when using RISC-V vector as
target.

a;
b() {
  long *c = 0;
  int *d;
  for (; a; ++a)
    c[a] = d[-a];
}

Compiled with

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d \
  -c -Ofast --param=riscv-autovec-preference=scalable \
  testcase.c

Output is

testcase.c:1:1: warning: data definition has no type or storage class
    1 | a;
      | ^
testcase.c:1:1: warning: type defaults to 'int' in declaration of 'a'
[-Wimplicit-int]
testcase.c:2:1: warning: return type defaults to 'int' [-Wimplicit-int]
    2 | b() {
      | ^
during RTL pass: expand
testcase.c: In function 'b':
testcase.c:6:10: internal compiler error: in expand_const_vector, at
config/riscv/riscv-v.cc:1510
    6 |     c[a] = d[-a];
      |     ~~~~~^~~~~~~
0x8e70b6 expand_const_vector
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:1510
0x14a4df4 riscv_vector::legitimize_move(rtx_def*, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:1524
0x184044f gen_movrvvm8qi(rtx_def*, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/vector.md:1054
0xc56b57 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*>(rtx_def*,
rtx_def*) const
        /home/jeremy/gittrees/mustang/gcc/gcc/recog.h:407
0xc56b57 emit_move_insn_1(rtx_def*, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:4164
0xc56f65 emit_move_insn(rtx_def*, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:4334
0xc2c4cd force_reg(machine_mode, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/explow.cc:693
0x14a2cee shuffle_generic_patterns
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3120
0x14a2cee expand_vec_perm_const_1
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3151
0x14a32b3 riscv_vector::expand_vec_perm_const(machine_mode, machine_mode,
rtx_def*, rtx_def*, rtx_def*, vec_perm_indices const&)
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3203
0xefe0ce expand_vec_perm_const(machine_mode, rtx_def*, rtx_def*,
int_vector_builder<poly_int<2u, long> > const&, machine_mode, rtx_def*)
        /home/jeremy/gittrees/mustang/gcc/gcc/optabs.cc:6508
0xc4f682 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10453
0xc53c58 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10805
0xc4cb7a expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier,
rtx_def**, bool)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:9010
0xc4cb7a expand_expr(tree_node*, rtx_def*, machine_mode, expand_modifier)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.h:310
0xc4cb7a expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:9345
0xc53c58 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10805
0xc6062d store_expr(tree_node*, rtx_def*, int, bool, bool)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:6325
0xc62201 expand_assignment(tree_node*, tree_node*, bool)
        /home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:6043
0xb1f05c expand_gimple_stmt_1
        /home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:3946
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

System information
------------------

Using built-in specs.
COLLECT_GCC=./riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=gf9d93f8cc24 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230807 (experimental) (gf9d93f8cc24)

[Bug middle-end/110950] RISC-V vector ICE in expand_const_vector

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

--- Comment #1 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Created attachment 55709
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55709&action=edit
Script to run the compilation

[Bug target/110950] RISC-V vector ICE in expand_const_vector

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Confirm. Will fix it soon.
Thanks for report.

[Bug target/110950] RISC-V vector ICE in expand_const_vector

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Fix patch here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626795.html

[Bug target/110950] RISC-V vector ICE in expand_const_vector

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:c4d618143048ac781f435638ef6e788ba870dc53

commit r14-3099-gc4d618143048ac781f435638ef6e788ba870dc53
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed Aug 9 20:18:40 2023 +0800

    RISC-V: Support NPATTERNS = 1 stepped vector[PR110950]

    This patch fix ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

    0x1cf8939 expand_const_vector
            ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1587

            PR target/110950

    gcc/ChangeLog:

            * config/riscv/riscv-v.cc (expand_const_vector): Add NPATTERNS = 1
            stepped vector support.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr110950.c: New test.

[Bug target/110950] RISC-V vector ICE in expand_const_vector

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Patch resolves the issue.