[Bug c/110985] New: RISC-V: Incorrect code gen for RVV VLS

[Bug c/110985] New: RISC-V: Incorrect code gen for RVV VLS

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

            Bug ID: 110985
           Summary: RISC-V: Incorrect code gen for RVV VLS
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Given we have the below sample code.

#include <stdint.h>

typedef int16_t vnx16i __attribute__ ((vector_size (32)));

void
foo (int16_t *__restrict out)
{
  vnx16i v = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0};
  *(vnx16i *) out = v;
}

It will generate below incorrect asm when compile with "-march=rv64gcv -O3
--param=riscv-autovec-preference=fixed-vlmax".

foo:
        ret

In fact it may be something similar to below assembly code.

foo:
        vsetivli        zero, 16, e16, m2, ta, ma
        vid.v   v8
        vrsub.vi        v8, v8, 15
        vse16.v v8, (a0)
        ret

[Bug target/110985] RISC-V: Incorrect code gen for RVV VLS

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-08-11
             Status|UNCONFIRMED                 |NEW

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed, the store is missing from expand ...

[Bug target/110985] RISC-V: Incorrect code gen for RVV VLS

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Fix patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627119.html

[Bug target/110985] RISC-V: Incorrect code gen for RVV VLS

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:685abdb4a1fe46a12da5cc9ae1d5aaef9344a339

commit r14-3173-g685abdb4a1fe46a12da5cc9ae1d5aaef9344a339
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Aug 11 16:45:26 2023 +0800

    RISC-V: Fix vec_series expander[PR110985]

    This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

    gcc/ChangeLog:
            PR target/110985
            * config/riscv/riscv-v.cc (expand_vec_series): Refactor the
expander.

    gcc/testsuite/ChangeLog:
            PR target/110985
            * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: New test.

[Bug target/110985] RISC-V: Incorrect code gen for RVV VLS

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

Li Pan <pan2.li at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Li Pan <pan2.li at intel dot com> ---
Close this bug as committed already.