[Bug middle-end/110994] New: RISC-V Fortran: Illegal instruction ICE with scalable autovec

[Bug middle-end/110994] New: RISC-V Fortran: Illegal instruction ICE with scalable autovec

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

            Bug ID: 110994
           Summary: RISC-V Fortran: Illegal instruction ICE with scalable
                    autovec
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55723
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55723&action=edit
Fortran 90 source code of the test case

Discovered by accident when hunting down a RVV bug, but this appears to be
connected with the autovectorizer generically rather than specifically the
RISC-V vector ISA extension.

The following code (testcase.f90) causes an ICE when using RISC-V as target
with
--param=riscv-autovec-preference=scalable.

SUBROUTINE d(e) f

(this is invalid Fortran 90, but it should still not trigger an ICE)

Compiled with:

riscv64-unknown-linux-gnu-gfortran -march=rv64gc -mabi=lp64d -c \
    -Ofast --param=riscv-autovec-preference=scalable testcase.f90

Output is:

f951: internal compiler error: Illegal instruction
0x112a263 crash_signal
        /home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:314
0x7f0d57e3c4af ???
        ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x9342a9 poly_int_pod<2u, unsigned short>::to_constant() const
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv.cc:6565
0x9342a9 riscv_hard_regno_nregs
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv.cc:6578
0x1092519 init_reg_modes_target()
        /home/jeremy/gittrees/mustang/gcc/gcc/reginfo.cc:466
0xd00827 init_emit_regs()
        /home/jeremy/gittrees/mustang/gcc/gcc/emit-rtl.cc:6072
0x9e6058 backend_init
        /home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:1749
0x9e6058 do_compile
        /home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:2108
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

System information
------------------

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g68783211f66 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230811 (experimental) (g68783211f66)

[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |juzhe.zhong at rivai dot ai

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
confirm and fix patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627219.html

[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:9890f377013cf1e4f5b9fab8a7287a5380dade1f

commit r14-3177-g9890f377013cf1e4f5b9fab8a7287a5380dade1f
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sat Aug 12 10:30:02 2023 +0800

    RISC-V: Add TAREGT_VECTOR check into VLS modes

    This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

    This is caused VLS modes incorrect codes int register allocation.

    The original case trigger the ICE is fortran code but I can reproduce
    with a C code.

    gcc/ChangeLog:

            PR target/110994
            * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.

    gcc/testsuite/ChangeLog:

            PR target/110994
            * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test.

[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #3 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Confirmed the patch resolves this issue, and the code correctly produces a
syntax error.