[Bug middle-end/111296] New: RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[Bug middle-end/111296] New: RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

            Bug ID: 111296
           Summary: RISC-V vector: ICE in lra_split_hard_reg_for during
                    reload pass
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

The following issue was identified while attempting to compile SPEC CPU 2017
641.leela_s benchmark.

Reproducer (test.cc):

struct a
{
  int b;
  int c;
};
int d;
a
e ()
{
  a f;
  int g = d - 1, h = d / 2 - 1;
  f.b = g;
  f.c = h;
  return f;
}

Compiled with:

riscv64-unknown-linux-gnu-g++ -std=c++03 -march=rv64gcv -mabi=lp64d -c \
    -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable \
    test.cpp

Output is:

test.cpp: In function 'a e()':
test.cpp:15:1: error: unable to find a register to spill
   15 | }
      | ^
test.cpp:15:1: error: this is the insn:
(insn 59 69 68 2 (set (subreg:V2SI (reg:DI 181) 0)
        (if_then_else:V2SI (unspec:V2BI [
                    (const_vector:V2BI [
                            (const_int 1 [0x1]) repeated x2
                        ])
                    (const_int 2 [0x2]) repeated x3
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (plus:V2SI (reg:V2SI 182 [141])
                (const_vector:V2SI [
                        (const_int -1 [0xffffffffffffffff]) repeated x2
                    ]))
            (unspec:V2SI [
                    (reg:SI 0 zero)
                ] UNSPEC_VUNDEF))) "test.cpp":15:1 3122 {pred_addv2si}
     (expr_list:REG_DEAD (reg:V2SI 182 [141])
        (expr_list:REG_DEAD (reg:SI 67 vtype)
            (expr_list:REG_DEAD (reg:SI 66 vl)
                (expr_list:REG_DEAD (reg:SI 0 zero)
                    (nil))))))
during RTL pass: reload
test.cpp:15:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1861
0x9bab61 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0x1203e80 lra_split_hard_reg_for()
        /home/jeremy/gittrees/mustang/gcc/gcc/lra-assigns.cc:1861
0x11fdaf5 lra(_IO_FILE*)
        /home/jeremy/gittrees/mustang/gcc/gcc/lra.cc:2495
0x11b4dd9 do_reload
        /home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:5970
0x11b4dd9 execute
        /home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:6156
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.


System information
------------------

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g8451fbd5687 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230904 (experimental) (g8451fbd5687)

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

--- Comment #1 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Created attachment 55844
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55844&action=edit
Testcase (test.cpp)

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |juzhe.zhong at rivai dot ai

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
confirm

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:6b96de22d6bcadb45530c1898b264e4738afa4fd

commit r14-3744-g6b96de22d6bcadb45530c1898b264e4738afa4fd
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed Sep 6 22:28:03 2023 +0800

    RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

    This patch fix incorrect mode tieable between DI and V2SI which cause ICE
    in RA.

    gcc/ChangeLog:

            PR target/111296
            * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
            tieable for RVV modes.

    gcc/testsuite/ChangeLog:

            PR target/111296
            * g++.target/riscv/rvv/base/pr111296.C: New test.

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
I can confirm this patch resolves the issue.