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* [Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass
@ 2023-09-12 16:32 jeremy.bennett at embecosm dot com
2023-09-16 9:55 ` [Bug middle-end/111391] " cvs-commit at gcc dot gnu.org
2023-09-19 15:11 ` jeremy.bennett at embecosm dot com
0 siblings, 2 replies; 3+ messages in thread
From: jeremy.bennett at embecosm dot com @ 2023-09-12 16:32 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
Bug ID: 111391
Summary: RISC-V Vector: ICE in lra_split_hard_reg_for during
reload pass
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: jeremy.bennett at embecosm dot com
Target Milestone: ---
Created attachment 55885
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55885&action=edit
Reproducer
This looks like a reappearance of
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296. Found when investigating
failure of SPEC CPU 2017 600_perlbench_s to compile.
Reproducer (test.c)
int d ();
typedef struct
{
int b;
} c;
int
e (char *f, long g)
{
f += g;
while (g--)
*--f = d;
}
int
d (c * f)
{
while (h ())
switch (f->b)
case 'Q':
{
long a;
e (&a, sizeof (a));
i (a);
}
}
Compile with:
riscv64-unknown-linux-gnu-gcc -Wno-int-conversion -Wno-implicit-function \
-Wno-incompatible-pointer-types -Wno-implicit-function-declaration \
-march=rv64gcv -mabi=lp64d -c -Ofast -ftree-vectorize \
--param=riscv-autovec-preference=scalable test.c
Output is:
test.c: In function 'd':
test.c:25:1: error: unable to find a register to spill
25 | }
| ^
test.c:25:1: error: this is the insn:
(insn 49 48 58 5 (set (subreg:V8QI (reg:DI 158) 0)
(if_then_else:V8QI (unspec:V8BI [
(const_vector:V8BI [
(const_int 1 [0x1]) repeated x8
])
(const_int 8 [0x8])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(vec_duplicate:V8QI (reg:QI 155))
(unspec:V8QI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "test.c":23:2 1450 {*pred_broadcastv8qi}
(expr_list:REG_DEAD (reg:QI 155)
(expr_list:REG_DEAD (reg:SI 67 vtype)
(expr_list:REG_DEAD (reg:SI 66 vl)
(expr_list:REG_DEAD (reg:SI 0 zero)
(nil))))))
during RTL pass: reload
test.c:25:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1861
0x904fbb _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0xf35590 lra_split_hard_reg_for()
/home/jeremy/gittrees/mustang/gcc/gcc/lra-assigns.cc:1861
0xf2f205 lra(_IO_FILE*)
/home/jeremy/gittrees/mustang/gcc/gcc/lra.cc:2495
0xee6519 do_reload
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:5970
0xee6519 execute
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:6156
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
System information
------------------
Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g35f498d8dfc --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
-mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2 -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230912 (experimental) (g35f498d8dfc)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug middle-end/111391] RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass
2023-09-12 16:32 [Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass jeremy.bennett at embecosm dot com
@ 2023-09-16 9:55 ` cvs-commit at gcc dot gnu.org
2023-09-19 15:11 ` jeremy.bennett at embecosm dot com
1 sibling, 0 replies; 3+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-09-16 9:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:
https://gcc.gnu.org/g:86451305d8b2a25e7c6ea6c2f1ee69c419cba3ef
commit r14-4077-g86451305d8b2a25e7c6ea6c2f1ee69c419cba3ef
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Thu Sep 14 18:49:52 2023 +0800
RISC-V: Expand VLS mode to scalar mode move[PR111391]
This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
PR target/111391
gcc/ChangeLog:
* config/riscv/autovec.md (@vec_extract<mode><vel>): Remove @.
(vec_extract<mode><vel>): Ditto.
* config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
(pass_vsetvl::local_eliminate_vsetvl_insn): Fix bug.
* config/riscv/riscv.cc (riscv_legitimize_move): Expand VLS mode to
scalar mode move.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
* gcc.target/riscv/rvv/autovec/pr111391-1.c: New test.
* gcc.target/riscv/rvv/autovec/pr111391-2.c: New test.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug middle-end/111391] RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass
2023-09-12 16:32 [Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass jeremy.bennett at embecosm dot com
2023-09-16 9:55 ` [Bug middle-end/111391] " cvs-commit at gcc dot gnu.org
@ 2023-09-19 15:11 ` jeremy.bennett at embecosm dot com
1 sibling, 0 replies; 3+ messages in thread
From: jeremy.bennett at embecosm dot com @ 2023-09-19 15:11 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #2 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Confirm this issue is now resolved. Thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-09-12 16:32 [Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass jeremy.bennett at embecosm dot com
2023-09-16 9:55 ` [Bug middle-end/111391] " cvs-commit at gcc dot gnu.org
2023-09-19 15:11 ` jeremy.bennett at embecosm dot com
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