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From: "wilco at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed Date: Tue, 31 Oct 2023 16:51:26 +0000 [thread overview] Message-ID: <bug-111416-4-5VJt71zSwR@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-111416-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://gcc.gnu.org/bugzill | |a/show_bug.cgi?id=111235 --- Comment #3 from Wilco <wilco at gcc dot gnu.org> --- Fixed by commit r14-4365-g0731889c026bfe8d55c4851422ca5ec9d037f7a0 #include <stdatomic.h> #include <stdint.h> int64_t f (_Atomic int64_t *p) { return atomic_load (p); } now generates with -O2 -mcpu=cortex-a15: dmb ish ldrd r0, r1, [r0] dmb ish bx lr
next prev parent reply other threads:[~2023-10-31 16:51 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 " luke.geeson at cs dot ucl.ac.uk 2023-09-14 16:58 ` [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 " wilco at gcc dot gnu.org 2023-10-31 16:50 ` wilco at gcc dot gnu.org 2023-10-31 16:51 ` wilco at gcc dot gnu.org [this message] 2023-10-31 16:52 ` sjames at gcc dot gnu.org
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