[Bug c/111450] New: RISC-V: Missed optimized for strided load/store with stride = element width

[Bug c/111450] New: RISC-V: Missed optimized for strided load/store with stride = element width

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111450

            Bug ID: 111450
           Summary: RISC-V: Missed optimized for strided load/store with
                    stride = element width
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

Consider this following cases:

https://godbolt.org/z/3MPoz5q6x

#include "riscv_vector.h"

void foo (int8_t *in, int8_t *out, int n)
{
    vint8m1_t v = __riscv_vlse8_v_i8m1 (in, 1, n);
    __riscv_vsse8_v_i8m1 (out, 1, v, n);
}

void foo1 (int16_t *in, int16_t *out, int n)
{
    vint16m1_t v = __riscv_vlse16_v_i16m1 (in, 2, n);
    __riscv_vsse16_v_i16m1 (out, 2, v, n);
}

void foo3 (int32_t *in, int32_t *out, int n)
{
    vint32m1_t v = __riscv_vlse32_v_i32m1 (in, 4, n);
    __riscv_vsse32_v_i32m1 (out, 4, v, n);
}

void foo4 (int64_t *in, int64_t *out, int n)
{
    vint64m1_t v = __riscv_vlse64_v_i64m1 (in, 8, n);
    __riscv_vsse64_v_i64m1 (out, 8, v, n);
}

ASM:

foo:
        li      a5,1
        vsetvli zero,a2,e8,m1,ta,ma
        vlse8.v v1,0(a0),a5
        vsse8.v v1,0(a1),a5
        ret
foo1:
        li      a5,2
        vsetvli zero,a2,e16,m1,ta,ma
        vlse16.v        v1,0(a0),a5
        vsse16.v        v1,0(a1),a5
        ret
foo3:
        li      a5,4
        vsetvli zero,a2,e32,m1,ta,ma
        vlse32.v        v1,0(a0),a5
        vsse32.v        v1,0(a1),a5
        ret
foo4:
        li      a5,8
        vsetvli zero,a2,e64,m1,ta,ma
        vlse64.v        v1,0(a0),a5
        vsse64.v        v1,0(a1),a5
        ret


When stride = element width, vlse should be optimized into vle.
vsse should be optimized into vse.v.

So we can save a constant move instruction.

[Bug target/111450] RISC-V: Missed optimized for strided load/store with stride = element width

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111450

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Li Xu <xuli@gcc.gnu.org>:

https://gcc.gnu.org/g:47065ff360292c683670efb96df4b61f57dc1d9a

commit r14-4190-g47065ff360292c683670efb96df4b61f57dc1d9a
Author: xuli <xuli1@eswincomputing.com>
Date:   Thu Sep 21 03:04:56 2023 +0000

    RISC-V: Optimized for strided load/store with stride == element
width[PR111450]

    When stride == element width, vlsse should be optimized into vle.v.
    vsse should be optimized into vse.v.

            PR target/111450

    gcc/ChangeLog:

            * config/riscv/constraints.md (c01): const_int 1.
            (c02): const_int 2.
            (c04): const_int 4.
            (c08): const_int 8.
            * config/riscv/predicates.md (vector_eew8_stride_operand): New
predicate for stride operand.
            (vector_eew16_stride_operand): Ditto.
            (vector_eew32_stride_operand): Ditto.
            (vector_eew64_stride_operand): Ditto.
            * config/riscv/vector-iterators.md: New iterator for stride
operand.
            * config/riscv/vector.md: Add stride = element width constraint.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr111450.c: New test.

[Bug target/111450] RISC-V: Missed optimized for strided load/store with stride = element width

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111450

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Fixed on trunk.