[Bug middle-end/111548] New: RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

[Bug middle-end/111548] New: RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

            Bug ID: 111548
           Summary: RISC-V Vector: ICE in validate_change_or_fail (vsetvl
                    pass)
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55973
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55973&action=edit
Reproducer source code

This issue was identified building SPEC CPU 2017 602.gcc_s.

Reproducer (test.c):

a, c, d;
*b;
h() {
  int e;
  i();
  for (;;) {
    unsigned f;
    char *g;
    f = a;
    for (; f; f--) {
      if (*g == '"')
        e = !e;
      *b = g++;
    }
    if (c)
      break;
    f = d;
    for (; d;)
      if (e)
        b++;
  }
}

Compile with:

riscv64-unknown-linux-gnu-gcc -w -march=rv64gcv -mabi=lp64d -c -Ofast \
    -ftree-vectorize --param=riscv-autovec-preference=scalable test.c

Output is:
during RTL pass: vsetvl
test.c: In function 'h':
test.c:22:1: internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-vsetvl.cc:788
   22 | }
      | ^
0xa6ef0b validate_change_or_fail
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:788
0xa6f0bb validate_change_or_fail
        /home/jeremy/gittrees/mustang/gcc/gcc/hash-set.h:64
0xa6f0bb change_insn
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:804
0x165d292 pass_vsetvl::earliest_fusion()
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3415
0x165da61 pass_vsetvl::vsetvl_fusion()
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3457
0x165f950 pass_vsetvl::lazy_vsetvl()
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4373
0x165fad1 pass_vsetvl::execute(function*)
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4413
0x165fad1 pass_vsetvl::execute(function*)
        /home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4394
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

System information
==================

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g59d27cc55a0 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230923 (experimental) (g59d27cc55a0)

[Bug middle-end/111548] RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:9d5f20fc4a6b3254d2d379309193da4be2747987

commit r14-4248-g9d5f20fc4a6b3254d2d379309193da4be2747987
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sun Sep 24 11:17:01 2023 +0800

    RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]

    This patch fixes that AVL/VL reg incorrect fetch in VSETVL PASS.

    C/C++ regression passed.

    But gfortran didn't run yet. I am still finding a way to run it.

    Will commit it when I pass the fortran regression.

            PR target/111548

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p):
Bugfix

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr111548.c: New test.

[Bug middle-end/111548] RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #2 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Confirmed that the test now passes, as indeed does SPEC CPU 2017 602.gcc_s.

Thanks for the fix. Marking as resolved.