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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error
Date: Mon, 09 Oct 2023 01:12:13 +0000	[thread overview]
Message-ID: <bug-111621-4-gjzu8Yix0o@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-111621-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |juzhe.zhong at rivai dot ai

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
I don't think this is a bug.

You are using  __riscv_vadd_vx_i32m4_m.

The vd is not necessary same as vs2 and this intrinsic is supposed to use
TAMA which means that the tailed element and mask-inactive elements are
agnostic (can be either all ones or original value).

So the codegen is correct even though -O0 result is different from -O2/-O3.

If you want to use make vd same as vs2, you should use these following
intrinsics:

__riscv_vadd_vx_i32m4_tu
__riscv_vadd_vx_i32m4_mu
__riscv_vadd_vx_i32m4_tumu

      parent reply	other threads:[~2023-10-09  1:12 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-28  7:36 [Bug middle-end/111621] New: " mumuxi_ll at outlook dot com
2023-09-28 20:34 ` [Bug middle-end/111621] " pinskia at gcc dot gnu.org
2023-10-08  4:11 ` mumuxi_ll at outlook dot com
2023-10-09  1:12 ` juzhe.zhong at rivai dot ai [this message]

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