[Bug target/111947] New: RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[Bug target/111947] New: RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

            Bug ID: 111947
           Summary: RISC-V vector: RTL Check: expected code 'reg', have
                    'const_int' in rhs_regno, at rtl.h:1934
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56184
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56184&action=edit
-freport-bug output

Ran into an ICE with glibc with rtl checking enabled.

Bisected to/caused by commit: r14-4773-g29331e72d0c

during RTL pass: vsetvl
inet_ntop.c: In function 'inet_ntop':
inet_ntop.c:65:1: internal compiler error: RTL check: expected code 'reg', have
'const_int' in rhs_regno, at rtl.h:1934
   65 | }
      | ^
0x961683 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        ../../../gcc/gcc/rtl.cc:770
0x99934c rhs_regno(rtx_def const*)
        ../../../gcc/gcc/rtl.h:1934
0x999dec rhs_regno(rtx_def const*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2628
0x999dec pre_vsetvl::compute_lcm_local_properties()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2695
0x1734a89 pre_vsetvl::earliest_fuse_vsetvl_info()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2885
0x1735e29 pass_vsetvl::lazy_vsetvl()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3524
0x17361b7 pass_vsetvl::execute(function*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3571
0x17361b7 pass_vsetvl::execute(function*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3554

Reduced testcase from a glibc build failure:

char *a;
b() {
  int c[2];
  int d = 0;
  for (; d < 16; d += 2)
    c[d / 2] = a[d | 1];
  if (c[0])
    for (;;)
      ;
}

[Bug target/111947] RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Testcase output on r14-4873-g02aa322c8c:
> ./riscv64-unknown-linux-gnu-gcc red.c -S -o test.S -O2
red.c:2:1: warning: return type defaults to 'int' [-Wimplicit-int]
    2 | b() {
      | ^
during RTL pass: vsetvl
red.c: In function 'b':
red.c:10:1: internal compiler error: RTL check: expected code 'reg', have
'const_int' in rhs_regno, at rtl.h:1934
   10 | }
      | ^
0x961683 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        ../../../gcc/gcc/rtl.cc:770
0x99934c rhs_regno(rtx_def const*)
        ../../../gcc/gcc/rtl.h:1934
0x999dec rhs_regno(rtx_def const*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2628
0x999dec pre_vsetvl::compute_lcm_local_properties()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2695
0x1734a89 pre_vsetvl::earliest_fuse_vsetvl_info()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2885
0x1735e29 pass_vsetvl::lazy_vsetvl()
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3524
0x17361b7 pass_vsetvl::execute(function*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3571
0x17361b7 pass_vsetvl::execute(function*)
        ../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3554
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

[Bug target/111947] RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Lehua Ding <lhtin@gcc.gnu.org>:

https://gcc.gnu.org/g:7b2984ad76cac67b962eeb39eab62b6dacf7845e

commit r14-4876-g7b2984ad76cac67b962eeb39eab62b6dacf7845e
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Tue Oct 24 10:12:49 2023 +0800

    RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947]

    ICE on vsetvli a5, 8 instruction demand info.

    The AVL is const_int 8 which ICE on RENGO caller.

    Committed as it is obvious fix.

            PR target/111947

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc
(pre_vsetvl::compute_lcm_local_properties): Add REGNO check.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/vsetvl/pr111947.c: New test.

[Bug target/111947] RISC-V vector: RTL Check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Confirmed to be fixed on hash 7b2984ad76cac67b962eeb39eab62b6dacf7845e. Thanks
for the quick fix!