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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112092] RISC-V: Wrong RVV code produced for vsetvl-11.c and vsetvlmax-8.c Date: Thu, 26 Oct 2023 01:46:46 +0000 [thread overview] Message-ID: <bug-112092-4-wR9ThYpkyN@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-112092-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092 JuzheZhong <juzhe.zhong at rivai dot ai> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |juzhe.zhong at rivai dot ai --- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> --- No, it is correct. It's the fancy optimization we have done in VSETVL PASS. e16mf2 is same ratio e32m1. The later loop demand e32m1 and TU, so we fuse it into e16mf2 (__riscv_vsetvl_e16mf2(avl)), change it into e32m1 and TU. This is a valid optimization. You can change e16mf2 into e16m1. I am sure the fusion will be blocked.
next prev parent reply other threads:[~2023-10-26 1:46 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-26 1:00 [Bug target/112092] New: " macro at orcam dot me.uk 2023-10-26 1:46 ` juzhe.zhong at rivai dot ai [this message] 2023-10-26 1:57 ` [Bug target/112092] " juzhe.zhong at rivai dot ai 2023-10-26 4:01 ` macro at orcam dot me.uk 2023-10-26 6:38 ` kito at gcc dot gnu.org 2023-10-26 6:51 ` juzhe.zhong at rivai dot ai 2023-10-26 7:08 ` juzhe.zhong at rivai dot ai 2023-10-26 23:31 ` macro at orcam dot me.uk 2023-10-27 0:57 ` juzhe.zhong at rivai dot ai 2023-10-27 1:03 ` juzhe.zhong at rivai dot ai 2023-10-31 13:58 ` [Bug target/112092] RISC-V: Suboptimal " macro at orcam dot me.uk 2023-11-08 6:38 ` cvs-commit at gcc dot gnu.org 2023-11-08 6:39 ` juzhe.zhong at rivai dot ai
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