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* [Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms
@ 2023-10-29 17:40 rsandifo at gcc dot gnu.org
2023-10-29 17:41 ` [Bug rtl-optimization/112278] " rsandifo at gcc dot gnu.org
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2023-10-29 17:40 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278
Bug ID: 112278
Summary: lra: ICE in partial_subreg_p for mixture of AdvSIMD &
SVE register asms
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: rsandifo at gcc dot gnu.org
Target Milestone: ---
The following test, compiled with -march=armv8.2-a+sve, ICEs in
partial_subreg_p, called from new_insn_reg:
#include <arm_neon.h>
#include <arm_sve.h>
void
f (void)
{
{
register svint8_t v0 asm ("z0");
asm volatile ("" : "=w" (v0));
}
{
register int8x8x4_t v0 asm ("v0");
asm volatile ("" : "=w" (v0));
}
}
GCC 10 behaves similarly, so I don't think this is a regression.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug rtl-optimization/112278] lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms
2023-10-29 17:40 [Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms rsandifo at gcc dot gnu.org
@ 2023-10-29 17:41 ` rsandifo at gcc dot gnu.org
2023-12-05 9:21 ` cvs-commit at gcc dot gnu.org
2023-12-05 9:22 ` rsandifo at gcc dot gnu.org
2 siblings, 0 replies; 4+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2023-10-29 17:41 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278
Richard Sandiford <rsandifo at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed| |2023-10-29
Ever confirmed|0 |1
Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org
--- Comment #1 from Richard Sandiford <rsandifo at gcc dot gnu.org> ---
Testing a patch.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug rtl-optimization/112278] lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms
2023-10-29 17:40 [Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms rsandifo at gcc dot gnu.org
2023-10-29 17:41 ` [Bug rtl-optimization/112278] " rsandifo at gcc dot gnu.org
@ 2023-12-05 9:21 ` cvs-commit at gcc dot gnu.org
2023-12-05 9:22 ` rsandifo at gcc dot gnu.org
2 siblings, 0 replies; 4+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-12-05 9:21 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:
https://gcc.gnu.org/g:6e2e0ce6795c863e295eb33559f8dc0500297da3
commit r14-6139-g6e2e0ce6795c863e295eb33559f8dc0500297da3
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Tue Dec 5 09:20:55 2023 +0000
lra: Updates of biggest mode for hard regs [PR112278]
LRA keeps track of the biggest mode for both hard registers and
pseudos. The updates assume that the modes are ordered, i.e. that
we can tell whether one is no bigger than the other at compile time.
That is (or at least seemed to be) a reasonable restriction for pseudos.
But it isn't necessarily so for hard registers, since the uses of hard
registers can be logically distinct. The testcase is an example of this.
The biggest mode of hard registers is also special for other reasons.
As the existing comment says:
/* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
part of a multi-word register. In that case, just use the reg_rtx
mode. Do the same also if the biggest mode was larger than a register
or we can not compare the modes. Otherwise, limit the size to that of
the biggest access in the function or to the natural mode at least.
*/
This patch applies the same approach to the updates.
gcc/
PR rtl-optimization/112278
* lra-int.h (lra_update_biggest_mode): New function.
* lra-coalesce.cc (merge_pseudos): Use it.
* lra-lives.cc (process_bb_lives): Likewise.
* lra.cc (new_insn_reg): Likewise.
gcc/testsuite/
PR rtl-optimization/112278
* gcc.target/aarch64/sve/pr112278.c: New test.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug rtl-optimization/112278] lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms
2023-10-29 17:40 [Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms rsandifo at gcc dot gnu.org
2023-10-29 17:41 ` [Bug rtl-optimization/112278] " rsandifo at gcc dot gnu.org
2023-12-05 9:21 ` cvs-commit at gcc dot gnu.org
@ 2023-12-05 9:22 ` rsandifo at gcc dot gnu.org
2 siblings, 0 replies; 4+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2023-12-05 9:22 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278
Richard Sandiford <rsandifo at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|ASSIGNED |RESOLVED
--- Comment #3 from Richard Sandiford <rsandifo at gcc dot gnu.org> ---
Fixed on trunk.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-10-29 17:40 [Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms rsandifo at gcc dot gnu.org
2023-10-29 17:41 ` [Bug rtl-optimization/112278] " rsandifo at gcc dot gnu.org
2023-12-05 9:21 ` cvs-commit at gcc dot gnu.org
2023-12-05 9:22 ` rsandifo at gcc dot gnu.org
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