[Bug target/112375] New: vget_set_lane_1.c fails

[Bug target/112375] New: vget_set_lane_1.c fails

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

            Bug ID: 112375
           Summary: vget_set_lane_1.c fails
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: testsuite-fail
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64-linux-gnu

FAIL: gcc.target/aarch64/vget_set_lane_1.c scan-assembler-times
ins\\\\tv0.s\\\\[1\\\\], v1.s\\\\[0\\\\] 3


We expected ins here but currently get:
        zip1    v0.2s, v0.2s, v1.2s
3 times.

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0
            Summary|vget_set_lane_1.c fails     |[14 Regression]
                   |                            |vget_set_lane_1.c fails
           Keywords|                            |missed-optimization

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
I almost positive it was caused by r14-3381-g27de9aa15214 Where the the
back-end decides to use zip1 instead of ins here for the vec_perm.

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
This simple patch fixes the issue but I have not tested it yet, basically it
moves the ins case before the zip:
```
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 5fd7063663c..8a9b89807e3 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -24890,6 +24890,8 @@ aarch64_expand_vec_perm_const_1 (struct
expand_vec_perm_d *d)
            return true;
          else if (aarch64_evpc_dup (d))
            return true;
+         else if (aarch64_evpc_ins (d))
+           return true;
          else if (aarch64_evpc_zip (d))
            return true;
          else if (aarch64_evpc_uzp (d))
@@ -24898,8 +24900,6 @@ aarch64_expand_vec_perm_const_1 (struct
expand_vec_perm_d *d)
            return true;
          else if (aarch64_evpc_sel (d))
            return true;
-         else if (aarch64_evpc_ins (d))
-           return true;
          else if (aarch64_evpc_reencode (d))
            return true;

```

But maybe this needs some better cost mechanism because right now even though
we might be able to do ins because of reencoding zip might be detected first.

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

Tejas Belagod <belagod at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |belagod at gcc dot gnu.org
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2024-01-16
           Assignee|unassigned at gcc dot gnu.org      |belagod at gcc dot gnu.org
             Status|UNCONFIRMED                 |ASSIGNED

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

--- Comment #3 from Tejas Belagod <belagod at gcc dot gnu.org> ---
Confirmed.

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org>:

https://gcc.gnu.org/g:7d8585c0c0e5934780281abdee256ae6553e56e8

commit r14-9137-g7d8585c0c0e5934780281abdee256ae6553e56e8
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Thu Feb 22 15:32:08 2024 +0000

    AArch64: update vget_set_lane_1.c test output

    In the vget_set_lane_1.c test the following entries now generate a zip1
instead of an INS

    BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
    BUILD_TEST (int32x2_t,   int32x2_t,   , , s32, 1, 0)
    BUILD_TEST (uint32x2_t,  uint32x2_t,  , , u32, 1, 0)

    This is because the non-Q variant for indices 0 and 1 are just shuffling
values.
    There is no perf difference between INS SIMD to SIMD and ZIP on Arm uArches
but
    preferring the INS alternative has a drawback on all uArches as ZIP being a
three
    operand instruction can be used to tie the result to the return register
whereas
    INS would require an fmov.

    As such just update the test file for now.

    gcc/testsuite/ChangeLog:

            PR target/112375
            * gcc.target/aarch64/vget_set_lane_1.c: Update test output.

[Bug target/112375] [14 Regression] vget_set_lane_1.c fails

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed.