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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112598] RISC-V regression testsuite errors with rv64gcv_zvl512b
Date: Fri, 24 Nov 2023 02:37:48 +0000	[thread overview]
Message-ID: <bug-112598-4-Bj4KN3Kj0U@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-112598-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112598

--- Comment #9 from Li Pan <pan2.li at intel dot com> ---
Before tracer
------------------------------------------------------------- 
                        ENTRY
                           |
                       +-------+
                       |  B2   |
                       +-------+
                      /         \
                    a < 2        a >= 2
                    /              \ 
               +-----------+      +-----------+
               | vec store |----->| _3 = b[1] |
               +-----------+      +-----------+
                                  /            \
                                _3 != 1         _3 == 1
                                /                \
                            +--------+        +----------+
                            | abort  |        | return 0 |
                            +--------+        +----------+
After tracer
------------------------------------------------------------- 

                        ENTRY
                           |
                       +-------+
                       |  B2   |
                       +-------+
                      /         \
                    a < 2        a >= 2
                    /              \ 
            +-------------+      +-----------+
            | vec store   |      | _3 = b[1] |
            |             |      +-----------+
after tracer|             |       /            \
            |             |    _3 != 1         _3 == 1
            | _31 = b[1]  |     /                \
            +-------------+ +--------+        +----------+
                    |------>| abort  |        | return 0 |<---|
                    |       +--------+        +----------+    |
                    |                                         |
                    |-----------------------------------------|

After tracer, the vec store and scalar load will be in the same basic block and
unfortunately referenced to the same memory address. Thus, the sch1 make the
scalar load before vec store cause the failure on memory access sequeneces.

  parent reply	other threads:[~2023-11-24  2:37 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-17 21:18 [Bug target/112598] New: " patrick at rivosinc dot com
2023-11-17 21:21 ` [Bug target/112598] " patrick at rivosinc dot com
2023-11-21  2:43 ` juzhe.zhong at rivai dot ai
2023-11-21 13:38 ` cvs-commit at gcc dot gnu.org
2023-11-21 17:43 ` patrick at rivosinc dot com
2023-11-22  6:45 ` cvs-commit at gcc dot gnu.org
2023-11-22 11:09 ` juzhe.zhong at rivai dot ai
2023-11-22 12:31 ` cvs-commit at gcc dot gnu.org
2023-11-23  6:02 ` pan2.li at intel dot com
2023-11-24  2:37 ` pan2.li at intel dot com [this message]
2023-11-27  3:07 ` pan2.li at intel dot com
2023-11-27  8:15 ` rdapp at gcc dot gnu.org
2023-11-27  8:25 ` pan2.li at intel dot com
2023-11-27  8:43 ` rdapp at gcc dot gnu.org
2023-11-27 11:37 ` pan2.li at intel dot com
2023-11-27 12:42 ` rdapp at gcc dot gnu.org
2023-11-27 17:51 ` patrick at rivosinc dot com
2023-11-28  3:15 ` pan2.li at intel dot com
2023-12-04 21:35 ` patrick at rivosinc dot com
2023-12-11 23:48 ` patrick at rivosinc dot com
2024-01-24 23:53 ` patrick at rivosinc dot com

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