[Bug c/112743] New: RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[Bug c/112743] New: RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

            Bug ID: 112743
           Summary: RISC-V: building FAIL with -march=rv64(or
                    rv32)gc_zve32f_zvfh_zfh
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

/work/home/jzzhong/work/toolchain/riscv/newlib/newlib/libc/include/math.h:92:15:
internal compiler error: in simplify_subreg, at simplify-rtx.cc:7550
   92 | extern double modf (double, double *);
      |               ^~~~
  CC       libm/common/libm_a-sf_isnan.o
  CC       libm/common/libm_a-s_rint.o
  CC       libm/common/libm_a-s_logb.o
  CC       libm/common/libm_a-s_log2.o
  CC       libm/common/libm_a-s_fdim.o
  CC       libm/common/libm_a-sf_isnanf.o
  CC       libm/common/libm_a-s_fma.o
  CC       libm/common/libm_a-sf_log1p.o
0x18611cb simplify_context::simplify_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7550
0x18611cb simplify_context::simplify_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7550
0x186450b simplify_context::simplify_gen_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7875
0x186450b simplify_context::simplify_gen_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7875
0x186496e simplify_context::lowpart_subreg(machine_mode, rtx_def*,
machine_mode)
        ../../../../gcc/gcc/simplify-rtx.cc:7905
0x186496e simplify_context::lowpart_subreg(machine_mode, rtx_def*,
machine_mode)
        ../../../../gcc/gcc/simplify-rtx.cc:7905
0x18611cb simplify_context::simplify_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7550
0x18611cb simplify_context::simplify_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7550
0x186450b simplify_context::simplify_gen_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7875
0x186496e simplify_context::lowpart_subreg(machine_mode, rtx_def*,
machine_mode)
        ../../../../gcc/gcc/simplify-rtx.cc:7905
0x186450b simplify_context::simplify_gen_subreg(machine_mode, rtx_def*,
machine_mode, poly_int<2u, unsigned long>)
        ../../../../gcc/gcc/simplify-rtx.cc:7875
0x186496e simplify_context::lowpart_subreg(machine_mode, rtx_def*,
machine_mode)
        ../../../../gcc/gcc/simplify-rtx.cc:7905
  CC       libm/common/libm_a-s_fmax.o
  CC       libm/common/libm_a-s_fmin.o
  CC       libm/common/libm_a-s_fpclassify.o
  CC       libm/common/libm_a-s_lrint.o
0x10cfa74 lowpart_subreg(machine_mode, rtx_def*, machine_mode)
        ../../../../gcc/gcc/rtl.h:3565
0x10cfa74 lowpart_subreg(machine_mode, rtx_def*, machine_mode)
        ../../../../gcc/gcc/rtl.h:3565
0x10cfa74 lowpart_subreg(machine_mode, rtx_def*, machine_mode)
        ../../../../gcc/gcc/rtl.h:3565
0x10cfa74 lowpart_subreg(machine_mode, rtx_def*, machine_mode)
        ../../../../gcc/gcc/rtl.h:3565
  CC       libm/common/libm_a-sf_nan.o
  CC       libm/common/libm_a-s_llrint.o
  CC       libm/common/libm_a-s_lround.o
  CC       libm/common/libm_a-sf_nextafter.o
  CC       libm/common/libm_a-s_llround.o
0x124a13f gen_lowpart_common(machine_mode, rtx_def*)
        ../../../../gcc/gcc/emit-rtl.cc:1626
0x124a13f gen_lowpart_common(machine_mode, rtx_def*)
        ../../../../gcc/gcc/emit-rtl.cc:1626
0x124a13f gen_lowpart_common(machine_mode, rtx_def*)
        ../../../../gcc/gcc/emit-rtl.cc:1626
0x124a13f gen_lowpart_common(machine_mode, rtx_def*)
        ../../../../gcc/gcc/emit-rtl.cc:1626
  CC       libm/common/libm_a-s_nearbyint.o
  CC       libm/common/libm_a-s_remquo.o
  CC       libm/common/libm_a-s_round.o
0x17d7da2 gen_lowpart_general(machine_mode, rtx_def*)
        ../../../../gcc/gcc/rtlhooks.cc:48
0x17d7da2 gen_lowpart_general(machine_mode, rtx_def*)
        ../../../../gcc/gcc/rtlhooks.cc:48
0x17d7da2 gen_lowpart_general(machine_mode, rtx_def*)
        ../../../../gcc/gcc/rtlhooks.cc:48
0x17d7da2 gen_lowpart_general(machine_mode, rtx_def*)
        ../../../../gcc/gcc/rtlhooks.cc:48
  CC       libm/common/libm_a-sf_pow10.o
0x1c7c6f9 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
        ../../../../gcc/gcc/config/riscv/riscv.cc:2619
0x1c7c6f9 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
        ../../../../gcc/gcc/config/riscv/riscv.cc:2619
0x1c7c6f9 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
        ../../../../gcc/gcc/config/riscv/riscv.cc:2619
0x1c7c6f9 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
        ../../../../gcc/gcc/config/riscv/riscv.cc:2619


This is an serious BUG need to be addressed.

[Bug c/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

Li Pan <pan2.li at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |pan2.li at intel dot com

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
Thanks Juzhe, will take a look at this issue and keep you posted.

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|c                           |target
   Last reconfirmed|                            |2023-11-28
     Ever confirmed|0                           |1
             Target|                            |riscv
           Keywords|                            |ice-on-valid-code
             Status|UNCONFIRMED                 |WAITING

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
No testcase.

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:25a51e98fdd504826a40775a5e5b9ffb336b5aa1

commit r14-5945-g25a51e98fdd504826a40775a5e5b9ffb336b5aa1
Author: Pan Li <pan2.li@intel.com>
Date:   Wed Nov 29 14:31:30 2023 +0800

    RISC-V: Bugfix for ICE in block move when zve32f

    The exact_div requires the exactly multiple of the divider.
    Unfortunately, the condition will be broken when zve32f in
    some cases. For example,

    potential_ew is 8
    BYTES_PER_RISCV_VECTOR * lmul1 is [4, 4]

    This patch would like to ensure the precondition of exact_div
    when get_vec_mode.

            PR target/112743

    gcc/ChangeLog:

            * config/riscv/riscv-string.cc (expand_block_move): Add
            precondition check for exact_div.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112743-1.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

--- Comment #4 from Li Pan <pan2.li at intel dot com> ---
There may be another ICE for zve32f, will double-check about the details.

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:e5bbeedcf7020dfa3870d11cf2b85bc048655698

commit r14-6068-ge5bbeedcf7020dfa3870d11cf2b85bc048655698
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Nov 30 15:08:50 2023 +0800

    RISC-V: Bugfix for legitimize move when get vec mode in zve32f

    If we want to extract 64bit value but ELEN < 64, we use RVV
    vector mode with EEW = 32 to extract the highpart and lowpart.
    However, this approach doesn't honor DFmode when movdf pattern
    when ZVE32f and of course results in ICE when zve32f.

    This patch would like to reuse the approach with some additional
    handing, consider lowpart bits is meaningless for FP mode, we need
    one int reg as bridge here. For example:

    rtx tmp = gen_rtx_reg (DImode)
    reg:DI = reg:DF (fmv.d.x) // Move DF reg to DI
    ...
    perform the extract for high and low parts
    ...
    reg:DF = reg:DI (fmv.x.d) // Move DI reg back to DF after all done

            PR target/112743

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_legitimize_move): Take the
            exist (U *mode) and handle DFmode like DImode when EEW is
            32bits for ZVE32F.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112743-2.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

--- Comment #6 from Li Pan <pan2.li at intel dot com> ---
Double confirmed the riscv-gnu-toolchain can be built successfully with the
latest newlib.

[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |RESOLVED
         Resolution|---                         |FIXED

--- Comment #7 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Fixed