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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b Date: Thu, 14 Dec 2023 16:54:01 +0000 [thread overview] Message-ID: <bug-112773-4-ecRj69tVHr@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-112773-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112773 --- Comment #14 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>: https://gcc.gnu.org/g:0a5170b5f596bb5fcedf25d93952b979d02d1f56 commit r14-6555-g0a5170b5f596bb5fcedf25d93952b979d02d1f56 Author: Robin Dapp <rdapp@ventanamicro.com> Date: Sun Dec 3 21:55:16 2023 +0100 expmed: Use GET_MODE_PRECISION and expander's output mode. This changes the vec_extract path of extract_bit_field to use GET_MODE_PRECISION instead of GET_MODE_BITSIZE and uses the mode obtained from insn_data[icode].operand[0] as target mode. Also, it adds a vec_extract<mode>bi expander for riscv that maps to vec_extract<mode>qi. This fixes an ICE on riscv where we did not find a vec_extract optab and continued with the generic code which requires 1-byte alignment that riscv mask modes do not provide. Apart from that it adds poly_int support to riscv's vec_extract expander and makes the RVV..BImode -> QImode expander call emit_vec_extract in order not to duplicate code. gcc/ChangeLog: PR target/112773 * config/riscv/autovec.md (vec_extract<mode>bi): New expander calling vec_extract<mode>qi. * config/riscv/riscv-protos.h (riscv_legitimize_poly_move): Export. (emit_vec_extract): Change argument from poly_int64 to rtx. * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns): Ditto. * config/riscv/riscv.cc (riscv_legitimize_poly_move): Export. (riscv_legitimize_move): Use rtx instead of poly_int64. * expmed.cc (store_bit_field_1): Change BITSIZE to PRECISION. (extract_bit_field_1): Change BITSIZE to PRECISION and use return mode from insn_data as target mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/pr112773.c: New test.
next prev parent reply other threads:[~2023-12-14 16:54 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-30 3:10 [Bug target/112773] New: " patrick at rivosinc dot com 2023-11-30 8:46 ` [Bug target/112773] " rguenth at gcc dot gnu.org 2023-11-30 9:06 ` juzhe.zhong at rivai dot ai 2023-11-30 17:10 ` patrick at rivosinc dot com 2023-12-01 1:57 ` juzhe.zhong at rivai dot ai 2023-12-01 2:01 ` juzhe.zhong at rivai dot ai 2023-12-01 2:02 ` juzhe.zhong at rivai dot ai 2023-12-01 2:05 ` patrick at rivosinc dot com 2023-12-01 2:05 ` juzhe.zhong at rivai dot ai 2023-12-01 10:27 ` rdapp at gcc dot gnu.org 2023-12-01 11:54 ` rdapp at gcc dot gnu.org 2023-12-01 12:07 ` rguenth at gcc dot gnu.org 2023-12-01 12:44 ` rdapp at gcc dot gnu.org 2023-12-01 13:20 ` rguenther at suse dot de 2023-12-01 21:16 ` rdapp at gcc dot gnu.org 2023-12-14 16:54 ` cvs-commit at gcc dot gnu.org [this message] 2023-12-14 19:51 ` patrick at rivosinc dot com 2023-12-14 20:13 ` rdapp at gcc dot gnu.org 2023-12-14 21:09 ` patrick at rivosinc dot com
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