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From: "vineetg at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112817] RISC-V: RVV: provide a preprocessor macro for VLS codegen
Date: Fri, 01 Dec 2023 23:22:27 +0000 [thread overview]
Message-ID: <bug-112817-4-YcPQsw1zqA@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-112817-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817
--- Comment #6 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #5)
> Support VLS codegen with -mrvv-vector-bits and attribute is reasonable to be
> landed on GCC-14.
I don't think that is the reqmt for this issue. Just defining the preprocessor
flag with existing gcc toggle for VLS codegen should be enough - as long as it
generates same macro as llvm.
next prev parent reply other threads:[~2023-12-01 23:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 21:50 [Bug target/112817] New: " vineetg at gcc dot gnu.org
2023-12-01 21:51 ` [Bug target/112817] " pinskia at gcc dot gnu.org
2023-12-01 21:53 ` pinskia at gcc dot gnu.org
2023-12-01 21:55 ` pinskia at gcc dot gnu.org
2023-12-01 21:57 ` vineetg at gcc dot gnu.org
2023-12-01 22:01 ` pinskia at gcc dot gnu.org
2023-12-01 22:31 ` juzhe.zhong at rivai dot ai
2023-12-01 23:22 ` vineetg at gcc dot gnu.org [this message]
2023-12-01 23:24 ` juzhe.zhong at rivai dot ai
2023-12-05 15:59 ` kito at gcc dot gnu.org
2024-01-08 23:18 ` vineetg at gcc dot gnu.org
2024-01-08 23:21 ` [Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits " juzhe.zhong at rivai dot ai
2024-01-08 23:41 ` pinskia at gcc dot gnu.org
2024-01-10 11:35 ` juzhe.zhong at rivai dot ai
2024-01-11 16:15 ` vineetg at gcc dot gnu.org
2024-03-06 18:23 ` vineetg at gcc dot gnu.org
2024-03-06 18:25 ` vineetg at gcc dot gnu.org
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