public inbox for gcc-bugs@sourceware.org
help / color / mirror / Atom feed
* [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
@ 2023-12-04 22:50 patrick at rivosinc dot com
2023-12-05 6:54 ` [Bug target/112851] " juzhe.zhong at rivai dot ai
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: patrick at rivosinc dot com @ 2023-12-04 22:50 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112851
Bug ID: 112851
Summary: [14 Regression] RISCV ICE: vsetvl pass: in
partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: patrick at rivosinc dot com
Target Milestone: ---
Created attachment 56800
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56800&action=edit
-freport-bug output
Seen on rv32gcv_zvl{256|512|1024}b:
pr112755
pr112756
pr112757
FAIL: gcc.dg/torture/pr109219.c -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops -ftracer -finline-functions (internal compiler error: in
partial_subreg_p, at rtl.h:3187)
Command:
> /scratch/tc-testing/tc-dec-4-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv32gcv_zvl256b -mabi=ilp32d -O3 -funroll-loops -ftracer pr109219.c -freport-bug
during RTL pass: vsetvl
pr109219.c: In function 'g_97':
pr109219.c:21:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
21 | }
| ^
0xb3a42b partial_subreg_p(machine_mode, machine_mode)
../../../gcc/gcc/rtl.h:3187
0xb3a42b partial_subreg_p(machine_mode, machine_mode)
../../../gcc/gcc/rtl.h:3181
0xb3a42b
rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_info&,
rtl_ssa::insn_info*, rtx_obj_reference)
../../../gcc/gcc/rtl-ssa/insns.cc:524
0x23ee521
rtl_ssa::function_info::add_insn_to_block(rtl_ssa::function_info::build_info&,
rtx_insn*)
../../../gcc/gcc/rtl-ssa/insns.cc:662
0x2a0876d
rtl_ssa::function_info::add_block_contents(rtl_ssa::function_info::build_info&)
../../../gcc/gcc/rtl-ssa/blocks.cc:948
0x2a08e8a
rtl_ssa::function_info::start_block(rtl_ssa::function_info::build_info&,
rtl_ssa::bb_info*)
../../../gcc/gcc/rtl-ssa/blocks.cc:1064
0x2a08f1c
rtl_ssa::function_info::bb_walker::before_dom_children(basic_block_def*)
../../../gcc/gcc/rtl-ssa/blocks.cc:117
0x225c207 dom_walker::walk(basic_block_def*)
../../../gcc/gcc/domwalk.cc:311
0x2a0a5c9 rtl_ssa::function_info::process_all_blocks()
../../../gcc/gcc/rtl-ssa/blocks.cc:1281
0x23ebb68 rtl_ssa::function_info::function_info(function*)
../../../gcc/gcc/rtl-ssa/functions.cc:50
0x1734d12 pre_vsetvl::pre_vsetvl()
../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2218
0x1733527 pass_vsetvl::lazy_vsetvl()
../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3454
0x173391f pass_vsetvl::execute(function*)
../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3518
0x173391f pass_vsetvl::execute(function*)
../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3501
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /scratch/tmp/ccMXNexu.out file, please attach
this to your bugreport.
Testcase:
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/gcc.dg/torture/pr109219.c;h=2b5c514ad858e583e5f610101303429bcbf06780;hb=HEAD
Godbolt:
https://godbolt.org/z/PMjeGhzEz
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/112851] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
2023-12-04 22:50 [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b patrick at rivosinc dot com
@ 2023-12-05 6:54 ` juzhe.zhong at rivai dot ai
2023-12-05 7:33 ` rguenth at gcc dot gnu.org
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: juzhe.zhong at rivai dot ai @ 2023-12-05 6:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112851
--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Confirm. I will take a look at it.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/112851] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
2023-12-04 22:50 [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b patrick at rivosinc dot com
2023-12-05 6:54 ` [Bug target/112851] " juzhe.zhong at rivai dot ai
@ 2023-12-05 7:33 ` rguenth at gcc dot gnu.org
2023-12-05 23:30 ` cvs-commit at gcc dot gnu.org
2023-12-06 19:00 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: rguenth at gcc dot gnu.org @ 2023-12-05 7:33 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112851
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |14.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/112851] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
2023-12-04 22:50 [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b patrick at rivosinc dot com
2023-12-05 6:54 ` [Bug target/112851] " juzhe.zhong at rivai dot ai
2023-12-05 7:33 ` rguenth at gcc dot gnu.org
@ 2023-12-05 23:30 ` cvs-commit at gcc dot gnu.org
2023-12-06 19:00 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-12-05 23:30 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112851
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:
https://gcc.gnu.org/g:2e7abd09621a4401d44f4513adf126bce4b4828b
commit r14-6197-g2e7abd09621a4401d44f4513adf126bce4b4828b
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue Dec 5 20:57:27 2023 +0800
RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and
BITS_PER_RISCV_VECTOR
This patch fixes ICE mentioned on PR112851 and PR112852.
Actually these ICEs happens many times in full coverage testing.
The ICE happens on:
bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
84 | }
| ^
0x11a7271 partial_subreg_p(machine_mode, machine_mode)
../../../../gcc/gcc/rtl.h:3187
gcc_checking_assert (ordered_p (outer_prec, inner_prec));
outer_prec is the PRECISION of RVVM1SImode
inner_prec is the PRECISION of V64SImode
when it is zvl512b.
outer_prec is VLA mode with size (512, 512)
inner_prec is VLS mode with size (2048, 0)
Their precision/size relationship is not certain.
So block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR,
then we never reaches
the situation that comparing the precision/size between VLA size and VLS
size that size > coeffs[0] of VLA mode.
Note this patch cause following regression:
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize
scan-assembler-not vset
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize
scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2
FAIL: gcc.target/riscv/rvv/base/cpymem-1.c check-function-bodies f3
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f2
FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f3
1. cpymem check FAIL should be fixed on the testcase since the test is
fragile which should be robostified.
2. pr111751.c is Vector cost model issue, and I will fix it in the
following patch.
For now, we should land this patch first (highest-priority) since it is
fixing ICE.
PR target/112851
PR target/112852
gcc/ChangeLog:
* config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes
according
TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Add LMUL = 8
option.
* gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-1.c: Adapt test.
* gcc.target/riscv/rvv/autovec/pr112851.c: New test.
* gcc.target/riscv/rvv/autovec/pr112852.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/112851] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b
2023-12-04 22:50 [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b patrick at rivosinc dot com
` (2 preceding siblings ...)
2023-12-05 23:30 ` cvs-commit at gcc dot gnu.org
@ 2023-12-06 19:00 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: patrick at rivosinc dot com @ 2023-12-06 19:00 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112851
Patrick O'Neill <patrick at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution|--- |FIXED
--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Fixed. Thank you!
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-12-06 19:00 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-04 22:50 [Bug target/112851] New: [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv32gcv_zvl256b patrick at rivosinc dot com
2023-12-05 6:54 ` [Bug target/112851] " juzhe.zhong at rivai dot ai
2023-12-05 7:33 ` rguenth at gcc dot gnu.org
2023-12-05 23:30 ` cvs-commit at gcc dot gnu.org
2023-12-06 19:00 ` patrick at rivosinc dot com
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).