[Bug target/112852] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv64gcv_zvl512b

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112852

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:2e7abd09621a4401d44f4513adf126bce4b4828b

commit r14-6197-g2e7abd09621a4401d44f4513adf126bce4b4828b
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Tue Dec 5 20:57:27 2023 +0800

    RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and
BITS_PER_RISCV_VECTOR

    This patch fixes ICE mentioned on PR112851 and PR112852.
    Actually these ICEs happens many times in full coverage testing.

    The ICE happens on:

    bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
       84 | }
          | ^
    0x11a7271 partial_subreg_p(machine_mode, machine_mode)
            ../../../../gcc/gcc/rtl.h:3187

    gcc_checking_assert (ordered_p (outer_prec, inner_prec));

    outer_prec is the PRECISION of RVVM1SImode
    inner_prec is the PRECISION of V64SImode

    when it is zvl512b.

    outer_prec is VLA mode with size (512, 512)
    inner_prec is VLS mode with size (2048, 0)

    Their precision/size relationship is not certain.
    So block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR,
then we never reaches
    the situation that comparing the precision/size between VLA size and VLS
size that size > coeffs[0] of VLA mode.

    Note this patch cause following regression:

    FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize 
scan-assembler-not vset
    FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize 
scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2

    FAIL: gcc.target/riscv/rvv/base/cpymem-1.c check-function-bodies f3
    FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f2
    FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f3

    1. cpymem check FAIL should be fixed on the testcase since the test is
fragile which should be robostified.

    2. pr111751.c is Vector cost model issue, and I will fix it in the
following patch.

    For now, we should land this patch first (highest-priority) since it is
fixing ICE.

            PR target/112851
            PR target/112852

    gcc/ChangeLog:

            * config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes
according
            TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Add LMUL = 8
option.
            * gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
            * gcc.target/riscv/rvv/autovec/zve32f-1.c: Adapt test.
            * gcc.target/riscv/rvv/autovec/pr112851.c: New test.
            * gcc.target/riscv/rvv/autovec/pr112852.c: New test.