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* [Bug target/112855] New: [14] RISC-V vector: overwriting stack args
@ 2023-12-05 5:21 patrick at rivosinc dot com
2023-12-05 18:54 ` [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value patrick at rivosinc dot com
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: patrick at rivosinc dot com @ 2023-12-05 5:21 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112855
Bug ID: 112855
Summary: [14] RISC-V vector: overwriting stack args
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: patrick at rivosinc dot com
Target Milestone: ---
reduced testcase:
int printf(char *, ...);
int a;
int b = 100;
int c[25];
int d;
int main() {
int e;
d = 0;
for (; d < 5; d++) {
e = 0;
for (; e < 5; e++)
c[d * 5 + e] = 0;
}
if (b)
if (a)
for (;;)
;
b++;
int volatile f = *c;
printf("%d\n", b);
}
Tested using qemu with these commands:
> ./bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -O3 red.c -o rv64gcv.out
> ./bin/riscv64-unknown-linux-gnu-gcc -march=rv64gc -mabi=lp64d -O3 red.c -o rv64gc.out
> QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,Zve32f=true,Zve64f=true ./bin/qemu-riscv64 rv64gc.out
101
> QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,Zve32f=true,Zve64f=true ./bin/qemu-riscv64 rv64gcv.out
5
rv64gcv should match rv64gc and output 101. I'm not sure where it's getting "5"
from.
When you comment out the b++, the behavior is fixed (and both rv64gcv and
rv64gc output 100):
https://godbolt.org/z/chqGo6fj8
Changing other aspects of the program will also fix the behavior, it's just
that commenting out b++ was the least-disruptive change on the assembly code
that I could find.
You can also set b to zero. I just have it at 100 to make it more obvious that
the arg is getting overwritten, not just added/subtracted.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value
2023-12-05 5:21 [Bug target/112855] New: [14] RISC-V vector: overwriting stack args patrick at rivosinc dot com
@ 2023-12-05 18:54 ` patrick at rivosinc dot com
2023-12-06 14:36 ` cvs-commit at gcc dot gnu.org
2023-12-06 18:54 ` patrick at rivosinc dot com
2 siblings, 0 replies; 4+ messages in thread
From: patrick at rivosinc dot com @ 2023-12-05 18:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112855
Patrick O'Neill <patrick at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|[14] RISC-V vector: Appears |[14] RISC-V vector:
|to be overwriting stack arg |vsetivli clobbers variable
| |value
--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
lw a5,%lo(b)(a3)
load the value of b (100) into a5
vsetivli a5,5,e32,m1,ta,ma
clobbers the a5 regsiter which previously held b
addiw a1,a5,1
a5 is treated as b (this is the b++ statement)
sw a1,%lo(b)(a3)
and a1 (a5+1) is stored to b.
It appears like the compiler doesn't realize that vsetivli clobbers a5.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value
2023-12-05 5:21 [Bug target/112855] New: [14] RISC-V vector: overwriting stack args patrick at rivosinc dot com
2023-12-05 18:54 ` [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value patrick at rivosinc dot com
@ 2023-12-06 14:36 ` cvs-commit at gcc dot gnu.org
2023-12-06 18:54 ` patrick at rivosinc dot com
2 siblings, 0 replies; 4+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-12-06 14:36 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112855
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:
https://gcc.gnu.org/g:c9d5b46a25547035e381b0246de5cb553ca8b02d
commit r14-6222-gc9d5b46a25547035e381b0246de5cb553ca8b02d
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Wed Dec 6 22:26:46 2023 +0800
RISC-V: Fix VSETVL PASS bug
As PR112855 mentioned, the VSETVL PASS insert vsetvli in unexpected
location.
Due to 2 reasons:
1. incorrect transparant computation LCM data. We need to check VL operand
defs and uses.
2. incorrect fusion of unrelated edge which is the edge never reach the
vsetvl expression.
PR target/112855
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::compute_lcm_local_properties): Fix transparant LCM
data.
(pre_vsetvl::earliest_fuse_vsetvl_info): Disable earliest fusion
for unrelated edge.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112855.c: New test.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value
2023-12-05 5:21 [Bug target/112855] New: [14] RISC-V vector: overwriting stack args patrick at rivosinc dot com
2023-12-05 18:54 ` [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value patrick at rivosinc dot com
2023-12-06 14:36 ` cvs-commit at gcc dot gnu.org
@ 2023-12-06 18:54 ` patrick at rivosinc dot com
2 siblings, 0 replies; 4+ messages in thread
From: patrick at rivosinc dot com @ 2023-12-06 18:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112855
Patrick O'Neill <patrick at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution|--- |FIXED
--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Confirmed to be fixed. Thank you!
^ permalink raw reply [flat|nested] 4+ messages in thread
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