[Bug target/112871] New: [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -03 rv32gc_zicond

[Bug target/112871] New: [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -03 rv32gc_zicond

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

            Bug ID: 112871
           Summary: [14 Regression] RISCV ICE: in extract_insn, at
                    recog.cc:2804 (unrecognizable insn) with -03
                    rv32gc_zicond
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56808
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56808&action=edit
-freport-bug output

Output:
> /scratch/tc-testing/tc-dec-4-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -mabi=ilp32d -march=rv32gc_zicond -O3 red.c -freport-bug
red.c: In function 'k':
red.c:17:1: error: unrecognizable insn:
   17 | }
      | ^
(insn 104 103 105 14 (set (reg:SI 214)
        (if_then_else:SI (ne:SI (reg:SI 134 [ i.5_1 ])
                (const_int 0 [0]))
            (reg:SI 134 [ i.5_1 ])
            (reg:SI 215))) "red.c":13:7 discrim 6 -1
     (nil))
during RTL pass: vregs
red.c:17:1: internal compiler error: in extract_insn, at recog.cc:2804
0xa27c0b _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0xa27c2d _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../../../gcc/gcc/rtl-error.cc:116
0xa26501 extract_insn(rtx_insn*)
        ../../../gcc/gcc/recog.cc:2804
0xedc05e instantiate_virtual_regs_in_insn
        ../../../gcc/gcc/function.cc:1610
0xedc05e instantiate_virtual_regs
        ../../../gcc/gcc/function.cc:1993
0xedc05e execute
        ../../../gcc/gcc/function.cc:2040
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /scratch/tmp/ccEMDYFG.out file, please attach
this to your bugreport.

Testcase:
short a, c;
int b, d, i;
volatile char e;
static int f[] = {1, 1};
long g;
int volatile h;
short(j)() { return b ? a : 0; }
void k() {
l:
  h;
  g = 0;
  for (; g <= 2; g++) {
    d | ((i || j() & (0 == f[g])) ^ i) && e;
    if (c)
      goto l;
  }
}

Godbolt:
https://godbolt.org/z/31TYfjevE

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -03 rv32gc_zicond

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -03 rv32gc_zicond

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Created attachment 56821
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56821&action=edit
testcase-2-freport-bug-output

Here's a different testcase that manifests the same error:
int a, b, d, e, c;
char *f;
static int g;
void h(long long i) {
  int *j = &g;
  ++*j;
k:
  if (c >> d) {
    e = a % b;
    (*j = i) && ++*j;
    *f |= 1;
    if (i)
      goto k;
  }
}

> /scratch/tc-testing/tc-dec-6-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv32gcv_zicond -mabi=ilp32d -O1 red.c -freport-bug
red.c: In function 'h':
red.c:15:1: error: unrecognizable insn:
   15 | }
      | ^
(insn 54 53 55 8 (set (reg:SI 192 [ g_lsm.9 ])
        (if_then_else:SI (ne:SI (reg:SI 136 [ _9 ])
                (const_int 0 [0]))
            (reg:SI 136 [ _9 ])
            (reg:SI 193))) -1
     (nil))
during RTL pass: vregs
red.c:15:1: internal compiler error: in extract_insn, at recog.cc:2812
0xa2a25d _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0xa2a27f _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../../../gcc/gcc/rtl-error.cc:116
0xa28b53 extract_insn(rtx_insn*)
        ../../../gcc/gcc/recog.cc:2812
0xedeaee instantiate_virtual_regs_in_insn
        ../../../gcc/gcc/function.cc:1611
0xedeaee instantiate_virtual_regs
        ../../../gcc/gcc/function.cc:1994
0xedeaee execute
        ../../../gcc/gcc/function.cc:2041
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /scratch/tmp/ccFI5hsr.out file, please attach
this to your bugreport.

This testcase is a bit simpler since all the logic is in one function. It also
throws an ice with -O1 instead of -O3 that the previous testcase needed.

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -01 rv32gc_zicond

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jeffreyalaw at gmail dot com

--- Comment #2 from Patrick O'Neill <patrick at rivosinc dot com> ---
Bisected to r14-3041-g18c453f0e63

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -01 rv32gc_zicond

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |law at gcc dot gnu.org
                 CC|                            |law at gcc dot gnu.org
           Priority|P3                          |P4

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -01 rv32gc_zicond

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |DUPLICATE

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Same path through the conditional move expansion code.

*** This bug has been marked as a duplicate of bug 113001 ***

[Bug target/112871] [14 Regression] RISCV ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -01 rv32gc_zicond

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112871

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:10cbfcd60f9e5bdbe486e1c0192e0f168d899b77

commit r14-9341-g10cbfcd60f9e5bdbe486e1c0192e0f168d899b77
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Wed Mar 6 09:50:44 2024 -0700

    [PR target/113001] Fix incorrect operand swapping in conditional move

    This bug totally fell off my radar.  Sorry about that.

    We have some special casing the conditional move expander to simplify a
    conditional move when comparing a register against zero and that same
register
    is one of the arms.

    Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or
(ne
    (reg) (const_int 0)) where reg is the false arm need not use the fully
    generalized conditional move, thus saving an instruction for those cases.

    In the NE case we swapped the operands, but didn't swap the condition,
which
    led to the ICE due to an unrecognized pattern.  THe backend actually has
    distinct patterns for those two cases.  So swapping the operands is neither
    needed nor advisable.

    Regression tested on rv64gc and verified the new tests pass.

    Pushing to the trunk.

            PR target/113001
            PR target/112871
    gcc/
            * config/riscv/riscv.cc (expand_conditional_move): Do not swap
            operands when the comparison operand is the same as the false
            arm for a NE test.

    gcc/testsuite
            * gcc.target/riscv/zicond-ice-3.c: New test.
            * gcc.target/riscv/zicond-ice-4.c: New test.