[Bug target/112872] New: [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b

[Bug target/112872] New: [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

            Bug ID: 112872
           Summary: [14 Regression] RISCV ICE: in
                    store_integral_bit_field, at expmed.cc:1049 with -03
                    rv64gcv_zvl1024b
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56809
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56809&action=edit
-freport-bug output

Output:
> /scratch/tc-testing/tc-dec-4-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -marc
red.c: In function 'e':
red.c:4:6: internal compiler error: in store_integral_bit_field, at
expmed.cc:1049
    4 | void e() {
      |      ^
0x9b17de store_integral_bit_field
        ../../../gcc/gcc/expmed.cc:1049
0x9b17de store_bit_field_1
        ../../../gcc/gcc/expmed.cc:884
0xe4c83d store_bit_field(rtx_def*, poly_int<2u, unsigned long>, poly_int<2u,
unsigned long>, poly_int<2u, unsigned long>, poly_int<2u, unsigned long>,
machine_mode, rtx_def*, bool, bool)
        ../../../gcc/gcc/expmed.cc:1193
0xe783e8 store_field
        ../../../gcc/gcc/expr.cc:8231
0xe768ba store_constructor(tree_node*, rtx_def*, int, poly_int<2u, long>, bool)
        ../../../gcc/gcc/expr.cc:7986
0xe791e8 expand_constructor
        ../../../gcc/gcc/expr.cc:9329
0xe641f8 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        ../../../gcc/gcc/expr.cc:11605
0xe649a9 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        ../../../gcc/gcc/expr.cc:11220
0xf99ff2 expand_normal(tree_node*)
        ../../../gcc/gcc/expr.h:319
0xf99ff2 expand_vec_cond_mask_optab_fn
        ../../../gcc/gcc/internal-fn.cc:3116
0xf99ff2 expand_VCOND_MASK
        ../../../gcc/gcc/internal-fn.def:235
0xd2cd07 expand_call_stmt
        ../../../gcc/gcc/cfgexpand.cc:2738
0xd2cd07 expand_gimple_stmt_1
        ../../../gcc/gcc/cfgexpand.cc:3881
0xd2cd07 expand_gimple_stmt
        ../../../gcc/gcc/cfgexpand.cc:4045
0xd31ca0 expand_gimple_basic_block
        ../../../gcc/gcc/cfgexpand.cc:6101
0xd33c36 execute
        ../../../gcc/gcc/cfgexpand.cc:6836
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Testcase:
int a, c;
char b;
short d;
void e() {
  for (; d; d++) {
    for (; c;)
      ;
    b = 3;
    for (; b; b = 0)
      if (a)
        break;
  }
}

Looks similar to pr112854, but on rv64gcv_zvl1024b.

Godbolt:
https://godbolt.org/z/dvad6njP4

[Bug target/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[14 Regression] RISCV ICE:  |[14 Regression] RISCV ICE:
                   |in                          |in
                   |store_integral_bit_field,   |store_integral_bit_field,
                   |at expmed.cc:1049 with -03  |at expmed.cc:1049 with -03
                   |rv64gcv_zvl1024b            |rv64gcv_zvl1024b
                   |                            |--param=riscv-autovec-prefe
                   |                            |rence=fixed-vlmax

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Whoops, looks like the command got cut off when copy-pasting. Here's the full
thing:
> /scratch/tc-testing/tc-dec-4-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3 red.c

[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0

[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Thanks.  Yes that's similar and also looks fixed by the introduction of the
vec_init expander.  Added this test case to the patch and will push it soon.

[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:056cce412862f8d9b56a40dfbcbc3f9fa7f92883

commit r14-6211-g056cce412862f8d9b56a40dfbcbc3f9fa7f92883
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Tue Dec 5 15:24:12 2023 +0100

    RISC-V: Add vec_init expander for masks [PR112854].

    PR112854 shows a problem on rv32 with zvl1024b.  During the course of
    expand_constructor we try to overlay/subreg a 64-element mask by a
    scalar (Pmode) register.  This works for zvl512b and its maximum of
    32 elements but fails for rv32 and 64 elements.

    To circumvent this this patch adds a vec_init expander for vector masks
    by initializing a QImode vector and comparing that against 0.

    gcc/ChangeLog:

            PR target/112854
            PR target/112872

            * config/riscv/autovec.md (vec_init<mode>qi): New expander.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112854.c: New test.
            * gcc.target/riscv/rvv/autovec/pr112872.c: New test.

[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Patrick O'Neill <patrick at rivosinc dot com> ---
Fixed. Thank you!