[Bug target/112906] New: [14 Regression] aarch64: ICE with SVE ACLE code at -O2

[Bug target/112906] New: [14 Regression] aarch64: ICE with SVE ACLE code at -O2

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

            Bug ID: 112906
           Summary: [14 Regression] aarch64: ICE with SVE ACLE code at -O2
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

The following appears to be a recent regression on the trunk:

$ cat t.c
#pragma GCC aarch64 "arm_sve.h"
int c;
long d;
void f() {
  unsigned char *b;
  svbool_t x = svptrue_b8();
  svuint32_t g;
  svuint8_t h, i;
  d = 0;
  for (; (int *)d < &c; d += 16) {
    h = svld1rq(x, &b[d]);
    g = svdot_lane(g, i, h, 3);
  }
  svst1_vnum(x, &c, 8, g);
}
$ gcc/xgcc -B gcc -c t.c -O2 -march=armv8.2-a+sve
t.c: In function ‘f’:
t.c:15:1: error: unrecognizable insn:
   15 | }
      | ^
(insn 55 13 56 3 (set (reg:DI 129)
        (post_inc:DI (reg:DI 100 [ ivtmp.14 ]))) "t.c":11:9 -1
     (expr_list:REG_INC (reg:DI 100 [ ivtmp.14 ])
        (nil)))
during RTL pass: sched1
t.c:15:1: internal compiler error: in extract_insn, at recog.cc:2812
0x745bc7 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.cc:108
0x745bfb _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.cc:116
0xe588cf extract_insn(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/recog.cc:2812
0xcbd363 scan_one_insn
        /home/alecop01/toolchain/src/gcc/gcc/ira-costs.cc:1546
0xcbd363 process_bb_for_costs
        /home/alecop01/toolchain/src/gcc/gcc/ira-costs.cc:1748
0xcbf607 find_costs_and_classes
        /home/alecop01/toolchain/src/gcc/gcc/ira-costs.cc:2032
0xcbfeb3 ira_set_pseudo_classes(bool, _IO_FILE*)
        /home/alecop01/toolchain/src/gcc/gcc/ira-costs.cc:2618
0x1caea5b alloc_global_sched_pressure_data
        /home/alecop01/toolchain/src/gcc/gcc/haifa-sched.cc:7201
0x1caea5b sched_init()
        /home/alecop01/toolchain/src/gcc/gcc/haifa-sched.cc:7356
0x1cb041f haifa_sched_init()
        /home/alecop01/toolchain/src/gcc/gcc/haifa-sched.cc:7368
0xea0c0f schedule_insns()
        /home/alecop01/toolchain/src/gcc/gcc/sched-rgn.cc:3524
0xea138f schedule_insns()
        /home/alecop01/toolchain/src/gcc/gcc/sched-rgn.cc:3518
0xea138f rest_of_handle_sched
        /home/alecop01/toolchain/src/gcc/gcc/sched-rgn.cc:3736
0xea138f execute
        /home/alecop01/toolchain/src/gcc/gcc/sched-rgn.cc:3846
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[14 Regression] aarch64:    |[14 Regression] aarch64:
                   |ICE with SVE ACLE code at   |ICE with SVE ACLE code at
                   |-O2                         |-O2 since
                   |                            |r14-3981-g0f1f6cf87
                 CC|                            |rsandifo at gcc dot gnu.org

--- Comment #1 from Alex Coplan <acoplan at gcc dot gnu.org> ---
FWIW, started with r14-3981-g0f1f6cf872a03d82ab1973780b37bb8572e96f58 :

commit 0f1f6cf872a03d82ab1973780b37bb8572e96f58                                 
Author: Richard Sandiford <richard.sandiford@arm.com>                           
Date:   Thu Sep 14 11:39:53 2023 +0100                                          

    aarch64: Coerce addresses to be suitable for LD1RQ

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Target Milestone|---                         |14.0
   Last reconfirmed|                            |2023-12-07
     Ever confirmed|0                           |1

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

auto_inc_dec pass produces:
```
(insn 23 22 25 3 (set (reg:V16QI 118 [ MEM <vector(16) unsigned char>
[(unsigned char * {ref-all})_29] ])
        (mem:V16QI (post_inc:DI (reg:DI 107 [ ivtmp.13 ])) [0 MEM <vector(16)
unsigned char> [(unsigned char * {ref-all})_29]+0 S16 A8]))
"/app/example.cpp":12:9 1321 {*aarch64_simd_movv16qi}
     (expr_list:REG_INC (reg:DI 107 [ ivtmp.13 ])
        (nil)))
```

Combine has:
```
(insn 27 26 66 3 (parallel [
            (set (reg:VNx16QI 119 [ h ])
                (vec_duplicate:VNx16QI (mem:V16QI (post_inc:DI (reg:DI 107 [
ivtmp.13 ])) [0 MEM <vector(16) unsigned char> [(unsigned char *
{ref-all})_29]+0 S16 A8])))
            (clobber (scratch:VNx16BI))
        ]) "/app/example.cpp":12:9 6406 {aarch64_vec_duplicate_vqvnx16qi_le}
     (expr_list:REG_INC (reg:DI 107 [ ivtmp.13 ])
        (nil)))
```

But then split1 does:
```
(insn 67 26 68 3 (set (reg:DI 126)
        (post_inc:DI (reg:DI 107 [ ivtmp.13 ]))) "/app/example.cpp":12:9 -1
     (expr_list:REG_INC (reg:DI 107 [ ivtmp.13 ])
        (nil)))
(insn 68 67 69 3 (set (reg:VNx16BI 127)
        (const_vector:VNx16BI repeat [
                (const_int 1 [0x1])
            ])) "/app/example.cpp":12:9 -1
     (nil))
(insn 69 68 66 3 (set (reg:VNx16QI 119 [ h ])
        (unspec:VNx16QI [
                (reg:VNx16BI 127)
                (mem:V16QI (reg:DI 126) [0 MEM <vector(16) unsigned char>
[(unsigned char * {ref-all})_29]+0 S16 A8])
            ] UNSPEC_LD1RQ)) "/app/example.cpp":12:9 -1
     (nil))
```

Which is totally bogus. You can't have a post_inc by itself ...

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |acoplan at gcc dot gnu.org

--- Comment #3 from Alex Coplan <acoplan at gcc dot gnu.org> ---
It looks like the splitter isn't expecting to see auto-inc addressing, but
looks like we could handle it there.  Testing a patch.

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |patch

--- Comment #4 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Patches posted (and approved subject to no further comments from Vlad):

https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640535.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640536.html

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alex Coplan <acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:bac33a522bb51e30729191e935f25c2b0a63e225

commit r14-6582-gbac33a522bb51e30729191e935f25c2b0a63e225
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri Dec 15 09:31:28 2023 +0000

    emit-rtl, lra: Move lra's emit_inc to emit-rtl.cc

    In PR112906 we ICE because we try to use force_reg to reload an
    auto-increment address, but force_reg can't do this.

    With the aim of fixing the PR by supporting reloading arbitrary
    addresses in pre-RA splitters, this patch generalizes
    lra-constraints.cc:emit_inc and makes it available to the rest of the
    compiler by moving the generalized version to emit-rtl.cc.

    We observe that the separate IN parameter to LRA's emit_inc is
    redundant, since the function is static and is only (statically) called
    once in lra-constraints.cc, with in == value.  As such, we drop the IN
    parameter and simplify the code accordingly.

    We wrap the emit_inc code in a virtual class to allow LRA to override
    how reload pseudos are created, thereby preserving the existing LRA
    behaviour as much as possible.

    We then add a second (higher-level) routine to emit-rtl.cc,
    force_reload_address, which can reload arbitrary addresses.  This uses
    the generalized emit_inc code to handle the RTX_AUTOINC case.  The
    second patch in this series uses force_reload_address to fix PR112906.

    Since we intend to call address_reload_context::emit_autoinc from within
    splitters, and the code lifted from LRA calls recog, we have to avoid
    clobbering recog_data.  We do this by introducing a new RAII class for
    saving/restoring recog_data on the stack.

    gcc/ChangeLog:

            PR target/112906
            * emit-rtl.cc (address_reload_context::emit_autoinc): New.
            (force_reload_address): New.
            * emit-rtl.h (struct address_reload_context): Declare.
            (force_reload_address): Declare.
            * lra-constraints.cc (class lra_autoinc_reload_context): New.
            (emit_inc): Drop IN parameter, invoke
            code moved to emit-rtl.cc:address_reload_context::emit_autoinc.
            (curr_insn_transform): Drop redundant IN parameter in call to
            emit_inc.
            * recog.h (class recog_data_saver): New.

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alex Coplan <acoplan@gcc.gnu.org>:

https://gcc.gnu.org/g:ef9754dfdf18a89de3da23c4f23365f4c2611367

commit r14-6583-gef9754dfdf18a89de3da23c4f23365f4c2611367
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri Dec 15 09:32:42 2023 +0000

    aarch64: Handle autoinc addresses in ld1rq splitter [PR112906]

    This patch uses the new force_reload_address routine added by the
    previous patch to fix PR112906.

    gcc/ChangeLog:

            PR target/112906
            * config/aarch64/aarch64-sve.md
(@aarch64_vec_duplicate_vq<mode>_le):
            Use force_reload_address to reload addresses that aren't suitable
for
            ld1rq in the pre-RA splitter.

    gcc/testsuite/ChangeLog:

            PR target/112906
            * gcc.target/aarch64/sve/acle/general/pr112906.c: New test.

[Bug target/112906] [14 Regression] aarch64: ICE with SVE ACLE code at -O2 since r14-3981-g0f1f6cf87

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112906

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #7 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Fixed.