[Bug target/112971] New: [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[Bug target/112971] New: [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

            Bug ID: 112971
           Summary: [14] RISC-V rv64gcv_zvl256b vector -O3: internal
                    compiler error: Segmentation fault signal terminated
                    program cc1
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

> /scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv_zvl256b -mabi=lp64d -O3 red.c -S
riscv64-unknown-linux-gnu-gcc: internal compiler error: Segmentation fault
signal terminated program cc1
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
See <https://gcc.gnu.org/bugs/> for instructions.

Testcase:
int a;
short b[9];
char c, d;
void e() {
  d = 0;
  for (;; d++) {
    if (b[d])
      break;
    a = 8;
    for (; a >= 0; a--) {
      char *f = &c;
      *f &= d == (a & d);
    }
  }
}

-freport bug doesn't seem to be working, so here's the GCC -v output:
> /scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with:
/scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/../gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv
--with-sysroot=/scratch/tc-testing/tc-dec-11-trunk/build-rv64gcv/sysroot
--with-pkgversion=geea25179d8d --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=../../gcc --enable-multilib --with-abi=lp64d --with-arch=rv64imafdc
--with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2   
-mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.0 20231211 (experimental) (geea25179d8d)

The issue goes away if I use --param=riscv-autovec-preference=fixed-vlmax.

Godbolt: https://godbolt.org/z/4ovbT6d77

[Bug target/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
I think it is the same issue that I asked Robin to take care of.

Robin, could you confirm whether they are same issue (infinite loop due to
SUBREG)?

[Bug target/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
It doesn't look like the same issue to me.  The other bug is related to TImode
handling in combination with mask registers.  I will also have a look at this
one.

[Bug target/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
In match.pd we do something like this:


;; Function e (e, funcdef_no=0, decl_uid=2751, cgraph_uid=1, symbol_order=4)


Pass statistics of "forwprop": ----------------

Matching expression match.pd:2771, gimple-match-2.cc:35
Matching expression match.pd:2774, gimple-match-1.cc:66
Matching expression match.pd:2781, gimple-match-2.cc:96
Aborting expression simplification due to deep recursion
Aborting expression simplification due to deep recursion
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
Applying pattern match.pd:6784, gimple-match-5.cc:1742
gimple_simplified to _53 = { 0, ... } & { 8, 7, 6, ... };
_63 = { 0, ... } & { -9, -8, -7, ... };
_52 = { 0, ... } & { 8, 7, 6, ... };
_74 = { 0, ... } & { -9, -8, -7, ... };
_38 = { 0, ... } & { 8, 7, 6, ... };
_40 = { 0, ... } & { -9, -8, -7, ... };
_55 = { 0, ... } & { 8, 7, 6, ... };
_57 = { 0, ... } & { -9, -8, -7, ... };
_65 = { 0, ... } & { 8, 7, 6, ... };
_72 = { 0, ... } & { -9, -8, -7, ... };
_32 = { 0, ... } & { 8, 7, 6, ... };
mask__6.19_61 = _32 == { 0, ... };

That doesn't look particularly backend related but we're trying to simplify a
mask so you never know...

[Bug target/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #4 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Maybe try to remove this ?

 /* (X & Y) == X becomes (X & ~Y) == 0.  */
 (simplify
  (cmp:c (bit_and:c @0 @1) @0)
  (cmp (bit_and @0 (bit_not! @1)) { build_zero_cst (TREE_TYPE (@0)); }))
 (simplify
  (cmp:c (convert@3 (bit_and (convert@2 @0) INTEGER_CST@1)) (convert @0))
  (if (INTEGRAL_TYPE_P (TREE_TYPE (@0))
       && INTEGRAL_TYPE_P (TREE_TYPE (@2))
       && INTEGRAL_TYPE_P (TREE_TYPE (@3))
       && TYPE_PRECISION (TREE_TYPE (@2)) == TYPE_PRECISION (TREE_TYPE (@0))
       && TYPE_PRECISION (TREE_TYPE (@3)) > TYPE_PRECISION (TREE_TYPE (@2))
       && !wi::neg_p (wi::to_wide (@1)))
   (cmp (bit_and @0 (convert (bit_not @1)))
        { build_zero_cst (TREE_TYPE (@0)); })))

[Bug target/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #5 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Yes that's what I just tried.  No infinite loop anymore then.  But that's not a
new simplification and looks reasonable so there must be something special for
our backend.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Looks like `{ 0, ... } & { -9, -8, -7, ... }` is not simplifying down to just
`{ 0, ...}`

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Can you modify:
```
/* x & 0 -> 0  */
(simplify
 (bit_and @0 integer_zerop@1)
 @1)
```
to
```
/* x & 0 -> 0  */
(simplify
 (bit_and:c @0 integer_zerop@1)
 @1)
```

That in theory should not matter but I don't think we simplify normally VLA
constants ...

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #8 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Yes, can confirm that this helps.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The real fix will be to const_binop .
Right now const_binop only handles a few cases for VLA's VECTOR_CST and it
seems like it really only handles +, -, and sometimes * and sometimes left shit
.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2023-12-12

--- Comment #10 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #11 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #9)
> The real fix will be to const_binop .
> Right now const_binop only handles a few cases for VLA's VECTOR_CST and it
> seems like it really only handles +, -, and sometimes * and sometimes left
> shit .

I should say for stepped VLA VECTOR_CST .
In this case have one fully dup 0 and'ed with a stepped VECTOR_CST and that is
not handled.

Maybe a few special cases are needed here for &, |, ^ might be enough.

BIT_AND_EXPR: handle both 0 and -1
BIT_IOR_EXPR: handle both 0 and -1
BIT_XOR_EXPR: handle 0

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #12 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Thanks Andrew.

Will you send the patch to fix this ICE for RISC-V ?
It's important for risc-v since it is ICE bug that we should land it in GCC-14
release.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #13 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #12)
> Thanks Andrew.
> 
> Will you send the patch to fix this ICE for RISC-V ?

I doubt I will have time to work on it really. I have not figured out just yet
to produce an ARMv9-a SVE testcase but maybe next week if I do figure that out,
I Might find  some time to work on it.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #14 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Oh, I just take a look again. It seems that the issue is fixed on the trunk ?

Hi, Patrick.

https://godbolt.org/z/f1rnsYxf9

Could you confirm it ?

If it is fixed, could you send a patch with the test ?

Thanks.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #15 from Patrick O'Neill <patrick at rivosinc dot com> ---
(In reply to JuzheZhong from comment #14)
> Oh, I just take a look again. It seems that the issue is fixed on the trunk ?
> 
> Hi, Patrick.
> 
> https://godbolt.org/z/f1rnsYxf9
> 
> Could you confirm it ?
> 
> If it is fixed, could you send a patch with the test ?
> 
> Thanks.

Yay! Will do - I'm a bit tied up today/tomorrow but I'll figure out what fixed
it/send a patch when I get the chance

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|FIXED                       |---
             Status|RESOLVED                    |NEW

--- Comment #16 from Patrick O'Neill <patrick at rivosinc dot com> ---
False alarm. Looks like the vls change (which also affected pr112773) made this
failure hidden on trunk. Adding -fno-vect-cost-model shows the issue:
https://godbolt.org/z/fe8ETverz

Trunk still has the issue.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #17 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Ok. Thanks for confirm it.

Hi, Andrew.

Is this following:

```
/* x & 0 -> 0  */
(simplify
 (bit_and @0 integer_zerop@1)
 @1)
```
to
```
/* x & 0 -> 0  */
(simplify
 (bit_and:c @0 integer_zerop@1)
 @1)
```

enough ? If it can fix our RISC-V ICE.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #18 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #17)
> Ok. Thanks for confirm it.
> enough ? If it can fix our RISC-V ICE.

No, that is actually the wrong place to fix it. This was just to see if that
would fix the issue.

The correct place to fix this is in const_binop, see comment #9 and comment #11
.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #19 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
OK. I think we can't reproduce same issue on ARM SVE since VNx8HI is poly size
[4,4] SI mode. Wheras, RVV with zvl256b is [8,8] SImode that ARM SVE never has
such size scalable SI mode.

I guess Robin is going to work on it and has some ideas to fix it.

Looking forward to Robin's comments.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #20 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Hi, Andrew.

I saw this code which seems to cause infinite loop:

  if (TREE_CODE (arg1) == VECTOR_CST
      && TREE_CODE (arg2) == VECTOR_CST
      && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)),
                   TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg2))))
    {
      tree type = TREE_TYPE (arg1);
      bool step_ok_p;
      if (VECTOR_CST_STEPPED_P (arg1)
          && VECTOR_CST_STEPPED_P (arg2))
        /* We can operate directly on the encoding if:

              a3 - a2 == a2 - a1 && b3 - b2 == b2 - b1
            implies
              (a3 op b3) - (a2 op b2) == (a2 op b2) - (a1 op b1)

           Addition and subtraction are the supported operators
           for which this is true.  */
        step_ok_p = (code == PLUS_EXPR || code == MINUS_EXPR);
      else if (VECTOR_CST_STEPPED_P (arg1))
        /* We can operate directly on stepped encodings if:

             a3 - a2 == a2 - a1
           implies:
             (a3 op c) - (a2 op c) == (a2 op c) - (a1 op c)

           which is true if (x -> x op c) distributes over addition.  */
        step_ok_p = distributes_over_addition_p (code, 1);
      else
        /* Similarly in reverse.  */
        step_ok_p = distributes_over_addition_p (code, 2);
      tree_vector_builder elts;
      if (!elts.new_binary_operation (type, arg1, arg2, step_ok_p))
        return NULL_TREE;
      unsigned int count = elts.encoded_nelts ();
      for (unsigned int i = 0; i < count; ++i)
        {
          tree elem1 = VECTOR_CST_ELT (arg1, i);
          tree elem2 = VECTOR_CST_ELT (arg2, i);

          tree elt = const_binop (code, elem1, elem2);

          /* It is possible that const_binop cannot handle the given
             code and return NULL_TREE */
          if (elt == NULL_TREE)
            return NULL_TREE;
          elts.quick_push (elt);
        }

      return elts.build ();
    }

Could you give me suggestions how to fix it?

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #21 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Hi, Robin.

Will you continue on this issue ?

I have seen a benchmark has the same ICE.

Thanks.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #22 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Yes,  going to the thread soon.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

--- Comment #23 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:660e17f00658b68115282e6de38243e3c6cc1ee2

commit r14-8430-g660e17f00658b68115282e6de38243e3c6cc1ee2
Author: Robin Dapp <rdapp.gcc@gmail.com>
Date:   Mon Jan 15 16:23:30 2024 +0100

    fold-const: Handle AND, IOR, XOR with stepped vectors [PR112971].

    Found in PR112971 this patch adds folding support for bitwise operations
    of const duplicate zero/one vectors with stepped vectors.
    On riscv we have the situation that a folding would perpetually continue
    without simplifying because e.g. {0, 0, 0, ...} & {7, 6, 5, ...} would
    not be folded to {0, 0, 0, ...}.

    gcc/ChangeLog:

            PR middle-end/112971

            * fold-const.cc (simplify_const_binop): New function for binop
            simplification of two constant vectors when element-wise
            handling is not necessary.
            (const_binop): Call new function.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112971.c: New test.

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED

--- Comment #24 from Patrick O'Neill <patrick at rivosinc dot com> ---
Resolved