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From: "liuhongt at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113345] miss optimization for psign{b,w,d}.
Date: Fri, 12 Jan 2024 02:30:34 +0000 [thread overview]
Message-ID: <bug-113345-4-jmtZ2mhpTB@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-113345-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113345
--- Comment #1 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
>
> maybe we can just refactor the pattern as blow, then combine can generate
> the pattern for us.
>
> 22115(define_insn "<ssse3_avx2>_psign<mode>3"
> 22116 [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x")
> 22117 (unspec:VI124_AVX2
> 22118 [(match_operand:VI124_AVX2 1 "register_operand" "0,x")
> (neg:VI124:(match_dup 1)
> 22119 (match_operand:VI124_AVX2 2 "vector_operand" "xja,xjm")]
> 22120 UNSPEC_PBLENDV))]
Not for VI2, but ok for VI14.
next prev parent reply other threads:[~2024-01-12 2:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-12 2:15 [Bug target/113345] New: " liuhongt at gcc dot gnu.org
2024-01-12 2:30 ` liuhongt at gcc dot gnu.org [this message]
2024-01-12 3:31 ` [Bug target/113345] " liuhongt at gcc dot gnu.org
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