[Bug c/113393] New: RISC-V: Full coverage test bugs for upstream 20240112

[Bug c/113393] New: RISC-V: Full coverage test bugs for upstream 20240112

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113393

            Bug ID: 113393
           Summary: RISC-V:  Full coverage test bugs for upstream 20240112
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

For the RV64 parts

Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.c-torture/execute/pr68532.c   -O0  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  execution test

Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

[Bug target/113393] RISC-V: Full coverage test bugs for upstream 20240112

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113393

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:0627d1f5340c693699ad36fa2b741ff11d6f026a

commit r14-7238-g0627d1f5340c693699ad36fa2b741ff11d6f026a
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Mon Jan 15 14:57:38 2024 +0800

    RISC-V: Fix attributes bug configuration of ternary instructions

    This patch fixes the following FAILs:

    Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
    FAIL: gcc.c-torture/execute/pr68532.c   -O0  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -O1  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -O2  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -O3 -g  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -Os  execution test
    FAIL: gcc.c-torture/execute/pr68532.c   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  execution test

    Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
    FAIL: gcc.dg/vect/pr60196-1.c execution test
    FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

    Running target
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
    FAIL: gcc.dg/vect/pr60196-1.c execution test
    FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

    Running target
riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
    FAIL: gcc.dg/vect/pr60196-1.c execution test
    FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

    The root cause is attributes of ternary intructions are incorrect which
cause AVL prop PASS and VSETVL PASS behave
    incorrectly.

    Tested no regression and committed.

            PR target/113393

    gcc/ChangeLog:

            * config/riscv/vector.md: Fix ternary attributes.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr113393-1.c: New test.
            * gcc.target/riscv/rvv/autovec/pr113393-2.c: New test.
            * gcc.target/riscv/rvv/autovec/pr113393-3.c: New test.

[Bug target/113393] RISC-V: Full coverage test bugs for upstream 20240112

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113393

Li Pan <pan2.li at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
Closed as fixed in upstream and validated.

[Bug target/113393] RISC-V: Full coverage test bugs for upstream 20240112

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113393

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0