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From: "rearnsha at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113510] [14 Regression] [ARM Thumb] ICE in extract_constrain_insn with CPU cortex-m23
Date: Wed, 24 Jan 2024 13:00:16 +0000 [thread overview]
Message-ID: <bug-113510-4-QMNMi4Deei@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-113510-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113510
--- Comment #6 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #5)
> Yes the peephole2 in thumb1.md looks wrong:
> ```
> ;; Reloading and elimination of the frame pointer can
> ;; sometimes cause this optimization to be missed.
> (define_peephole2
> [(set (match_operand:SI 0 "arm_general_register_operand" "")
> (match_operand:SI 1 "const_int_operand" ""))
> (set (match_dup 0)
> (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
> "TARGET_THUMB1
> && UINTVAL (operands[1]) < 1024
> && (UINTVAL (operands[1]) & 3) == 0"
> [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
> ""
> )
> ```
>
> Confirmed.
Since this is a peephole and we're dealing with hard regs, we can just use
"low_register_operand" as the predicate for operand 0.
next prev parent reply other threads:[~2024-01-24 13:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-19 22:56 [Bug rtl-optimization/113510] New: " thiago.bauermann at linaro dot org
2024-01-19 22:58 ` [Bug rtl-optimization/113510] " thiago.bauermann at linaro dot org
2024-01-19 23:00 ` thiago.bauermann at linaro dot org
2024-01-20 8:24 ` [Bug target/113510] [14 Regression ARM " pinskia at gcc dot gnu.org
2024-01-23 20:44 ` [Bug target/113510] [14 Regression] [ARM " vmakarov at gcc dot gnu.org
2024-01-24 0:53 ` pinskia at gcc dot gnu.org
2024-01-24 13:00 ` rearnsha at gcc dot gnu.org [this message]
2024-03-05 17:31 ` rearnsha at gcc dot gnu.org
2024-03-05 17:35 ` cvs-commit at gcc dot gnu.org
2024-03-05 17:37 ` rearnsha at gcc dot gnu.org
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