[Bug c/113538] New: [RISC-V] --param=riscv-vector-abi will fail some cases

[Bug c/113538] New: [RISC-V] --param=riscv-vector-abi will fail some cases

[yanzhang.wang at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113538

            Bug ID: 113538
           Summary: [RISC-V] --param=riscv-vector-abi will fail some cases
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: yanzhang.wang at intel dot com
  Target Milestone: ---

When removing the riscv-vector-abi, I found some cases failed. We can test it
by passing the arg to the tests like,

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over
-zvfhmin.c
index 1d82cc8de2d..0725ca69222 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 --param=riscv-vector-abi"
} */

 #include "riscv_vector.h"



The test result will be,

                === gcc tests ===

Schedule of variations:
    riscv-sim/-march=rv64gcv_zvfh/-mabi=lp64d/-mcmodel=medlow

Running target riscv-sim/-march=rv64gcv_zvfh/-mabi=lp64d/-mcmodel=medlow
Using /mnt/install/toolchains/gnu/share/dejagnu/baseboards/riscv-sim.exp as
board description file for target.
Using /mnt/install/toolchains/gnu/share/dejagnu/config/sim.exp as generic
interface file for target.
Using /mnt/install/toolchains/gnu/share/dejagnu/baseboards/basic-sim.exp as
board description file for target.
Using
/home/yanzhang/workspace/toolchains/gnu/gcc/gcc/testsuite/config/default.exp as
tool-and-target-specific interface fil
e.
Running
/home/yanzhang/workspace/toolchains/gnu/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
...
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e16,\\s*mf4,\\s*t
[au],\\s*m[au] 8
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e16,\\s*mf2,\\s*t
[au],\\s*m[au] 2
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vle16\\.v\\s+v[0-9]+,\\s*0\\([0-9ax]+\\) 7
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vse16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 6
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl1re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl2re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl4re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 3
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vl8re16\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs2r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 1
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs4r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 3
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c scan-assembler-times
vs8r\\.v\\s+v[0-9]+,\\s*0\\([a-x][0-9]+\\) 5


The failed test cases almost in rvv/base with same reason.

GCC commit: 57f611604e8bab67af6c0bcfe6ea88c001408412

[Bug target/113538] [RISC-V] --param=riscv-vector-abi will fail some cases

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113538

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:acc22d56e140220e7dc6c138918cb6754b6d1c0b

commit r14-8424-gacc22d56e140220e7dc6c138918cb6754b6d1c0b
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Thu Jan 25 21:06:09 2024 +0800

    RISC-V: remove param riscv-vector-abi. [PR113538]

    Also adjust some of the tests for scan-assembly. The behavior is the
    same as --param=riscv-vector-abi before.

    gcc/ChangeLog:

            PR target/113538
            * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
            (riscv_fntype_abi): Ditto.
            * config/riscv/riscv.opt: Ditto.

    gcc/testsuite/ChangeLog:

            PR target/113538
            * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix the asm
            check.
            * gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-1.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-2.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-3-run.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-3.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-args-4.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-error-1.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-return-run.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-return.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-call-variant_cc.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c:
Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-1.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c:
Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: Ditto.
            * gcc.target/riscv/rvv/base/abi-callee-saved-2.c: Ditto.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Ditto.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Ditto.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Ditto.
            * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: Ditto.
            * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: Ditto.
            * gcc.target/riscv/rvv/base/spill-10.c: Ditto.
            * gcc.target/riscv/rvv/base/spill-11.c: Ditto.
            * gcc.target/riscv/rvv/base/spill-9.c: Ditto.
            * gcc.target/riscv/rvv/base/tuple_vundefined.c: Ditto.
            * gcc.target/riscv/rvv/base/vcreate.c: Ditto.
            * gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
            * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
            * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
            * lib/target-supports.exp: Remove the flag.

    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>

[Bug target/113538] [RISC-V] --param=riscv-vector-abi will fail some cases

[yanzhang.wang at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113538

Yanzhang, Wang <yanzhang.wang at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from Yanzhang, Wang <yanzhang.wang at intel dot com> ---
The patch was merged.