[Bug target/113742] New: ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[Bug target/113742] New: ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

            Bug ID: 113742
           Summary: ICE: RTL check: expected elt 1 type 'i' or 'n', have
                    'e' (rtx set) in riscv_macro_fusion_pair_p, at
                    config/riscv/riscv.cc:8416 with -O2
                    -finstrument-functions -mtune=sifive-p600-series
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: riscv64-unknown-linux-gnu

Created attachment 57309
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57309&action=edit
reduced testcase

This might need RTL checking enabled.

Compiler output:
$ riscv64-unknown-linux-gnu-gcc -O2 -finstrument-functions
-mtune=sifive-p600-series testcase.c 
during RTL pass: sched2
testcase.c: In function 'foo':
testcase.c:1:17: internal compiler error: RTL check: expected elt 1 type 'i' or
'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at
config/riscv/riscv.cc:8416
    1 | void foo(void) {}
      |                 ^
0xad8030 rtl_check_failed_type2(rtx_def const*, int, int, int, char const*,
int, char const*)
        /repo/gcc-trunk/gcc/rtl.cc:761
0xb8d03e riscv_macro_fusion_pair_p
        /repo/gcc-trunk/gcc/config/riscv/riscv.cc:8416
0x2b933a4 sched_macro_fuse_insns
        /repo/gcc-trunk/gcc/sched-deps.cc:2859
0x2b933a4 sched_analyze_insn
        /repo/gcc-trunk/gcc/sched-deps.cc:2898
0x2b94099 deps_analyze_insn(deps_desc*, rtx_insn*)
        /repo/gcc-trunk/gcc/sched-deps.cc:3690
0x2b9718a sched_analyze(deps_desc*, rtx_insn*, rtx_insn*)
        /repo/gcc-trunk/gcc/sched-deps.cc:3843
0x16af378 compute_block_dependences
        /repo/gcc-trunk/gcc/sched-rgn.cc:2738
0x16af378 sched_rgn_compute_dependencies(int)
        /repo/gcc-trunk/gcc/sched-rgn.cc:3367
0x16b1c18 schedule_region
        /repo/gcc-trunk/gcc/sched-rgn.cc:3139
0x16b1c18 schedule_insns()
        /repo/gcc-trunk/gcc/sched-rgn.cc:3525
0x16b22bd schedule_insns()
        /repo/gcc-trunk/gcc/sched-rgn.cc:3511
0x16b22bd rest_of_handle_sched2
        /repo/gcc-trunk/gcc/sched-rgn.cc:3749
0x16b22bd execute
        /repo/gcc-trunk/gcc/sched-rgn.cc:3888
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ riscv64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-riscv64/bin/riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r14-8771-20240203001826-g4b7d4d8a4af-checking-yes-rtl-df-extra-riscv64/bin/../libexec/gcc/riscv64-unknown-linux-gnu/14.0.1/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl --with-isa-spec=2.2
--with-sysroot=/usr/riscv64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=riscv64-unknown-linux-gnu
--with-ld=/usr/bin/riscv64-unknown-linux-gnu-ld
--with-as=/usr/bin/riscv64-unknown-linux-gnu-as --disable-multilib
--disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r14-8771-20240203001826-g4b7d4d8a4af-checking-yes-rtl-df-extra-riscv64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.1 20240203 (experimental) (GCC)

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

--- Comment #1 from Kito Cheng <kito at gcc dot gnu.org> ---
Thanks, forward and assigned this to our (SiFive) engineer :)

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:7eac19be5f7dd92fcbcfe13f6edbb4f9bd45c15c

commit r14-8959-g7eac19be5f7dd92fcbcfe13f6edbb4f9bd45c15c
Author: Monk Chiang <monk.chiang@sifive.com>
Date:   Tue Feb 13 09:02:12 2024 -0700

    Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying
UNSPEC_AUIPC. [PR113742]

    gcc/ChangeLog:

            PR target/113742
            * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
            recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/pr113742.c: New test.

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Edwin Lu <ewlu@gcc.gnu.org>:

https://gcc.gnu.org/g:3232ebd91ed55b275b9d5a6e8355336382c4afd5

commit r14-9118-g3232ebd91ed55b275b9d5a6e8355336382c4afd5
Author: Edwin Lu <ewlu@rivosinc.com>
Date:   Tue Feb 20 13:53:40 2024 -0800

    RISC-V: Specify mtune and march for PR113742

    The testcase pr113742.c is failing for 32 bit targets due to the following
cc1
    error:
    cc1: error: ABI requries '-march=rv64'

    Specify '-march=rv64gc' with '-mtune=sifive-p600-series'

            PR target/113742

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/pr113742.c: change mcpu to mtune and add march

    Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

--- Comment #4 from Zdenek Sojka <zsojka at seznam dot cz> ---
I can confirm the supplied testcase no longer fails.

[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-series

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at gcc dot gnu.org
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #5 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Per c#4.