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From: "miro.kropacek at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/113779] Very inefficient m68k code generated for simple copy loop Date: Tue, 06 Feb 2024 12:58:30 +0000 [thread overview] Message-ID: <bug-113779-4-wOgI6oArVz@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-113779-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113779 --- Comment #5 from Miro Kropacek <miro.kropacek at gmail dot com> --- I have been told that one of the reasons why post-incrementing modes are not supported / preferred these days is that they halt the CPU pipeline (of course, totally not applicable on m68k). So with the offsets you can parallelize the movements while when post-incrementing the values of a1, you always have to wait for the previous instruction to finish. So I could understand that this has been changed but it definitely shouldn't be a change involving all possible CPUs.
next prev parent reply other threads:[~2024-02-06 12:58 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-05 21:07 [Bug c/113779] New: " miro.kropacek at gmail dot com 2024-02-05 21:20 ` [Bug target/113779] " pinskia at gcc dot gnu.org 2024-02-06 7:58 ` rguenth at gcc dot gnu.org 2024-02-06 8:16 ` miro.kropacek at gmail dot com 2024-02-06 12:47 ` mikpelinux at gmail dot com 2024-02-06 12:58 ` miro.kropacek at gmail dot com [this message] 2024-02-06 13:14 ` rguenth at gcc dot gnu.org 2024-02-17 0:39 ` hp at gcc dot gnu.org
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