[Bug target/113816] New: Using SVE bit op reduction for SLP

[Bug target/113816] New: Using SVE bit op reduction for SLP

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113816

            Bug ID: 113816
           Summary: Using SVE bit op reduction for SLP
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64

Take at `-march=armv9-a -O3`:
```
#define SIGN unsigned
#define TYPE int
#define SIZE 16

void sior(SIGN TYPE *a, SIGN TYPE *r)
{
  SIGN TYPE b = 0;
  b |= a[0];
  b |= a[1];
  b |= a[2];
  b |= a[3];
  b |= a[4];
  *r = b;
}


void sxor(SIGN TYPE *a, SIGN TYPE *r)
{
  SIGN TYPE b = 0;
  b ^= a[0];
  b ^= a[1];
  b ^= a[2];
  b ^= a[3];
  b ^= a[4];
  *r = b;
}

void sand(SIGN TYPE *a, SIGN TYPE *r)
{
  SIGN TYPE b = -1;
  b &= a[0];
  b &= a[1];
  b &= a[2];
  b &= a[3];
  b &= a[4];
  *r = b;
}
```

These could use the SVE reduction instructions to handle (neon) SLP reductions
in a similar way 64bit multi isntructions are being used.

That is for srio GCC should produce:
```
        ptrue   p7.s, vl4
        ldq     q31, [x0]
        orv     s30, p7, z31.s
        str     s30, [x1]
```
(Hopefully I did this correctly)