[Bug target/113913] New: [14] RISC-V: suboptimal code gen for intrinsic vcreate

[Bug target/113913] New: [14] RISC-V: suboptimal code gen for intrinsic vcreate

[ewlu at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913

            Bug ID: 113913
           Summary: [14] RISC-V: suboptimal code gen for intrinsic vcreate
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ewlu at rivosinc dot com
  Target Milestone: ---

godbolt: https://godbolt.org/z/svPsddaTd

Functions like 

vfloat16m2_t
test_vcreate_v_f16m1_f16m2 (vfloat16m1_t v0, vfloat16m1_t v1)
{
  return __riscv_vcreate_v_f16m1_f16m2 (v0, v1);
}

are generating code like

test_vcreate_v_f16m1_f16m2:
        vmv1r.v v11,v8
        vmv1r.v v10,v9
        vmv1r.v v8,v11
        vmv1r.v v9,v10
        ret

which should be optimized away into a nop like later functions in the testcase

test_vcreate_v_i64m2_i64m8:
        ret

[Bug target/113913] [14] RISC-V: suboptimal code gen for intrinsic vcreate

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2024-02-13
           Keywords|                            |ra

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
This looks like a subreg issue:
```
(insn 18 17 8 2 (set (reg:RVVM2SF 134 [ <retval> ])
        (if_then_else:RVVM2SF (unspec:RVVMF16BI [
                    (const_vector:RVVMF16BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg:DI 138)
                    (const_int 2 [0x2]) repeated x2
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (const_vector:RVVM2SF repeat [
                    (const_double:SF 0.0 [0x0.0p+0])
                ])
            (unspec:RVVM2SF [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "/app/example.c":12:10 3943
{*pred_broadcastrvvm2sf_imm}
     (expr_list:REG_DEAD (reg:DI 138)
        (expr_list:REG_DEAD (reg:SI 67 vtype)
            (expr_list:REG_DEAD (reg:SI 66 vl)
                (expr_list:REG_DEAD (reg:DI 0 zero)
                    (expr_list:REG_EQUAL (const_vector:RVVM2SF repeat [
                                (const_double:SF 0.0 [0x0.0p+0])
                            ])
                        (nil)))))))
(insn 8 18 9 2 (set (subreg:RVVM1SF (reg:RVVM2SF 134 [ <retval> ]) 0)
        (reg:RVVM1SF 139)) "/app/example.c":12:10 2591 {*movrvvm1sf_whole}
     (expr_list:REG_DEAD (reg:RVVM1SF 139)
        (nil)))
(insn 9 8 13 2 (set (subreg:RVVM1SF (reg:RVVM2SF 134 [ <retval> ]) [16, 16])
        (reg:RVVM1SF 140)) "/app/example.c":12:10 2591 {*movrvvm1sf_whole}
     (expr_list:REG_DEAD (reg:RVVM1SF 140)
        (nil)))
```

Confirmed. There are others like this too.

Though I wonder if we emit:
(clobber (reg:RVVM2SF 134 [ <retval> ]))
When expanding __riscv_vcreate_v_f32m1_f32m2 and friends. If that might help.

The other thing is init-reg gets in the way and adds:
```
(insn 17 16 18 2 (set (reg:DI 138)
        (unspec:DI [
                (const_int 8 [0x8])
            ] UNSPEC_VLMAX)) "/app/example.c":6:10 -1
     (nil))
(insn 18 17 8 2 (set (reg:RVVM2HF 134 [ <retval> ])
        (if_then_else:RVVM2HF (unspec:RVVMF8BI [
                    (const_vector:RVVMF8BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg:DI 138)
                    (const_int 2 [0x2]) repeated x2
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (const_vector:RVVM2HF repeat [
                    (const_double:HF 0.0 [0x0.0p+0])
                ])
            (unspec:RVVM2HF [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "/app/example.c":6:10 -1
     (expr_list:REG_EQUAL (const_vector:RVVM2HF repeat [
                (const_double:HF 0.0 [0x0.0p+0])
            ])
        (nil)))
```

[Bug target/113913] [14] RISC-V: suboptimal code gen for intrinsic vcreate

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
It's the known issue we are trying to fix it in GCC-15.

My colleague Lehua is taking care of it.

CCing Lehua.