[Bug target/113980] New: risc-v: unnecessary sign-extend after lw, and more

[Bug target/113980] New: risc-v: unnecessary sign-extend after lw, and more

[Simon.Richter at hogyros dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113980

            Bug ID: 113980
           Summary: risc-v: unnecessary sign-extend after lw, and more
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: Simon.Richter at hogyros dot de
  Target Milestone: ---

On RISC-V with -O3,

#include <stdint.h>

extern uint32_t volatile d;
extern uint8_t volatile o;

void f()
{
    uint32_t t;
    while((t = d) & 0x80000000)
        ;
    o = t;
}

generates

f:
        lui     a3,%hi(d)
.L2:
        lw      a5,%lo(d)(a3)
        sext.w  a4,a5
        blt     a5,zero,.L2
        andi    a4,a4,0xff
        lui     a5,%hi(o)
        sb      a4,%lo(o)(a5)
        ret

The result of the lw instruction is already sign-extended, so the sext.w
instruction is unnecessary in any case. It is extra unnecessary when the value
is subsequently truncated with an and instruction, which itself is unnecessary
for a sb instruction.

To keep this bug report focused, I'd limit the problem description to the
sign-extend -- if the others warrant opening extra bug reports, I can do that
as well.

[Bug target/113980] risc-v: unnecessary sign-extend after lw with volatile, and more

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113980

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Basically GCC does not optimize around a volatile memory load/stores which
causes artifacts like this.