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* [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
@ 2024-02-21 2:39 patrick at rivosinc dot com
2024-02-21 2:41 ` [Bug target/114028] " pinskia at gcc dot gnu.org
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: patrick at rivosinc dot com @ 2024-02-21 2:39 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028
Bug ID: 114028
Summary: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: patrick at rivosinc dot com
Target Milestone: ---
Testcase:
int a, d = 55003;
long c, h;
long e = 1;
char g;
short i;
int main() {
g = 0;
for (; g < 16; g += 1) {
d |= c;
short l = d;
i = l < 0 || a >> 4 ? d : a;
h = i - 8L;
e &= h;
}
if (e == 1)
return 0;
else
return 1;
}
Commands:
> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv_zvl256b -O3 red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 user-config.out
> echo $?
1
> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv_zvl256b -O2 red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
> echo $?
0
Discovered/tested using 61ab046a327 (not bisected)
Found using fuzzer
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
2024-02-21 2:39 [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 patrick at rivosinc dot com
@ 2024-02-21 2:41 ` pinskia at gcc dot gnu.org
2024-02-22 12:47 ` rdapp at gcc dot gnu.org
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: pinskia at gcc dot gnu.org @ 2024-02-21 2:41 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Works fine on aarch64 with SVE:
```
[apinski@xeond2 upstream-full-cross]$ ./install/bin/aarch64-linux-gnu-gcc -O3
t6.c -static -march=armv9-a+sve2 -fno-vect-cost-model
[apinski@xeond2 upstream-full-cross]$ ./install-qemu/bin/qemu-aarch64 a.out
;echo $?
0
```
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
2024-02-21 2:39 [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 patrick at rivosinc dot com
2024-02-21 2:41 ` [Bug target/114028] " pinskia at gcc dot gnu.org
@ 2024-02-22 12:47 ` rdapp at gcc dot gnu.org
2024-02-23 20:54 ` cvs-commit at gcc dot gnu.org
2024-02-27 0:20 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: rdapp at gcc dot gnu.org @ 2024-02-22 12:47 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028
--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
This is a target issue. It looks like we try to construct a "superword"
sequence when the element size is already == Pmode. Testing a patch.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
2024-02-21 2:39 [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 patrick at rivosinc dot com
2024-02-21 2:41 ` [Bug target/114028] " pinskia at gcc dot gnu.org
2024-02-22 12:47 ` rdapp at gcc dot gnu.org
@ 2024-02-23 20:54 ` cvs-commit at gcc dot gnu.org
2024-02-27 0:20 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2024-02-23 20:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:
https://gcc.gnu.org/g:85c12ae8b80902ed46c97f33dbb61533e07f2905
commit r14-9159-g85c12ae8b80902ed46c97f33dbb61533e07f2905
Author: Robin Dapp <rdapp@ventanamicro.com>
Date: Thu Feb 22 13:40:55 2024 +0100
RISC-V: Fix vec_init for simple sequences [PR114028].
For a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to
construct a "superword" of two "_a"s. This only works for modes < Pmode
when we can "shift and or" both halves into one Pmode register.
This patch disallows the optimization for inner_mode == Pmode and emits
a simple broadcast in such a case.
gcc/ChangeLog:
PR target/114028
* config/riscv/riscv-v.cc
(rvv_builder::can_duplicate_repeating_sequence_p):
Return false if inner mode is already Pmode.
(rvv_builder::is_all_same_sequence): New function.
(expand_vec_init): Emit broadcast if sequence is all same.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr114028.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
2024-02-21 2:39 [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 patrick at rivosinc dot com
` (2 preceding siblings ...)
2024-02-23 20:54 ` cvs-commit at gcc dot gnu.org
@ 2024-02-27 0:20 ` patrick at rivosinc dot com
3 siblings, 0 replies; 5+ messages in thread
From: patrick at rivosinc dot com @ 2024-02-27 0:20 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028
Patrick O'Neill <patrick at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #4 from Patrick O'Neill <patrick at rivosinc dot com> ---
Resolved.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-02-21 2:39 [Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 patrick at rivosinc dot com
2024-02-21 2:41 ` [Bug target/114028] " pinskia at gcc dot gnu.org
2024-02-22 12:47 ` rdapp at gcc dot gnu.org
2024-02-23 20:54 ` cvs-commit at gcc dot gnu.org
2024-02-27 0:20 ` patrick at rivosinc dot com
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