[Bug target/114202] New: [14] RISC-V rv64gcv: miscompile at -O3

[Bug target/114202] New: [14] RISC-V rv64gcv: miscompile at -O3

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202

            Bug ID: 114202
           Summary: [14] RISC-V rv64gcv: miscompile at -O3
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Testcase:
int printf(const char *, ...);
signed char a, d;
_Bool b;
signed char c[324];
int e;
int main() {
  c[63] = 50;
  for (int f = 0; f < 9; f++) {
    for (unsigned g = 0; g < 12; g++)
      for (char h = 0; h < 8; h++)
        e = a += c[g * 9];
    b = e ? d : 0;
  }
  printf("%d\n", a);
}

Commands:
> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -O3 -fwrapv red.c -o red.out
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
32
> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -O2 -fwrapv red.c -o red.out
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
16

With the overflows (-fwrapv) the expected value is 16.

Tested/found using r14-9084-g61ab046a327 (not bisected)

Found via fuzzer.

[Bug target/114202] [14] RISC-V rv64gcv: miscompile at -O3

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Looks similar to pr114200 so it might be related/duplicate.

[Bug target/114202] [14] RISC-V rv64gcv: miscompile at -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:59554a50be8ebbd52e8a6348a92110af182e1874

commit r14-9345-g59554a50be8ebbd52e8a6348a92110af182e1874
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Wed Mar 6 12:15:40 2024 +0100

    RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

    Three-operand instructions like vmacc are modeled with an implicit
    output reload when the output does not match one of the operands.  For
    this we use vmv.v.v which is subject to length masking.

    In a situation where the current vl is less than the full vlenb
    and the fma's result value is used as input for a vector reduction
    (which is never length masked) we effectively only reduce vl
    elements.  The masked-out elements are relevant for the
    reduction, though, leading to a wrong result.

    This patch replaces the vmv reloads by full-register reloads.

    gcc/ChangeLog:

            PR target/114200
            PR target/114202

            * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr114200.c: New test.
            * gcc.target/riscv/rvv/autovec/pr114202.c: New test.

[Bug target/114202] [14] RISC-V rv64gcv: miscompile at -O3

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |DUPLICATE

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Same as PR114200.

*** This bug has been marked as a duplicate of bug 114200 ***