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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug ipa/114247] RISC-V: miscompile at -O3 and IPA SRA
Date: Tue, 05 Mar 2024 23:29:09 +0000 [thread overview]
Message-ID: <bug-114247-4-TyWpOrrP3H@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114247-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114247
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Keywords| |ABI
Last reconfirmed| |2024-03-05
Component|target |ipa
Ever confirmed|0 |1
Summary|RISC-V: miscompile at -O3 |RISC-V: miscompile at -O3
| |and IPA SRA
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
I think this is an IPA SRA issue.
The IR looks like:
j.constprop.isra (65535);
That is wrong for signed short ...
If I try manually I get:
j12 (-1);
```
void j.constprop.isra (short int ISRA.10)
{
...
}
```
IS there another target where the upper bits of the register are defined?
next prev parent reply other threads:[~2024-03-05 23:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-05 22:12 [Bug target/114247] New: RISC-V: miscompile at -O3 patrick at rivosinc dot com
2024-03-05 23:29 ` pinskia at gcc dot gnu.org [this message]
2024-03-06 8:00 ` [Bug ipa/114247] RISC-V: miscompile at -O3 and IPA SRA rguenth at gcc dot gnu.org
2024-04-03 15:33 ` jamborm at gcc dot gnu.org
2024-04-04 12:12 ` jamborm at gcc dot gnu.org
2024-04-04 12:14 ` rdapp at gcc dot gnu.org
2024-04-04 13:04 ` rdapp at gcc dot gnu.org
2024-04-04 21:39 ` jamborm at gcc dot gnu.org
2024-04-04 21:44 ` patrick at rivosinc dot com
2024-04-05 16:26 ` jamborm at gcc dot gnu.org
2024-05-15 13:46 ` cvs-commit at gcc dot gnu.org
2024-05-15 13:47 ` jamborm at gcc dot gnu.org
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