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From: "rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114668] [14] RISC-V rv64gcv: miscompile at -O3
Date: Wed, 10 Apr 2024 15:35:25 +0000	[thread overview]
Message-ID: <bug-114668-4-kciKYfn0k3@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114668-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114668

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
This, again, seems to be a problem with bit extraction from masks.
For some reason I didn't add the VLS modes to the corresponding vec_extract
patterns.  With those in place the problem is gone because we go through the
expander which does the right thing.

I'm still checking what exactly goes wrong without those as there is likely a
latent bug.

  parent reply	other threads:[~2024-04-10 15:35 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-09 21:55 [Bug target/114668] New: " patrick at rivosinc dot com
2024-04-09 22:00 ` [Bug target/114668] " pinskia at gcc dot gnu.org
2024-04-10 15:35 ` rdapp at gcc dot gnu.org [this message]
2024-04-15 13:12 ` cvs-commit at gcc dot gnu.org
2024-04-15 13:17 ` rdapp at gcc dot gnu.org

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